Secuenciador dinámico para el control de movimiento de robot hexápodo en una arquitectura FPGA

2019 ◽  
pp. 18-25
Author(s):  
Mariana Natalia Ibarra-Bonilla ◽  
Fernando Sánchez-Texis ◽  
Raúl Eusebio-Grande ◽  
Fernando Julián Quiñones-Novelo
Keyword(s):  
Control System ◽  
Degrees Of Freedom ◽  
Pulse Generator ◽  
Serial Communication ◽  
Waiting Times ◽  
Description Language ◽  
Hardware Description ◽  
Logical State ◽  
Information Interchange ◽  
Movement Test

A hexapod robot control system hardware architecture is presented. The control system is integrated in an FPGA XC6SLX16-Spartan6. The design is developed using hardware description language, VHDL. A robust architecture, divided into three logical state machine blocks, is implemented in the FPGA. Block one consists of a serial communication system for the information interchange between the user and the FPGA. The second block corresponds to the sequential circuit and data manager in charge of controlling the functions of the entire architecture. The third block is an 18-channel PWM pulse generator with a progressive duty cycle change control to perform robot movements. The system is designed to allow the user to download a complex movements sequence by combining different positions and waiting times. The architecture allows to save up to 10 movements different sequences in the internal memory block. Additionally, it allows modifying any sequence in real time, without affecting the robot operation. The architecture controls 18 servomotors allowing 18 degrees of freedom to the robot. The performing and movement test of the robot are presented.

The Control of High Voltage Electrostatic Precipitator Based on EDA

2014 ◽  
Vol 910 ◽  
pp. 336-339
Author(s):  
Zi Sheng Zhang ◽  
Yi Wang ◽  
Chun Sheng Wang ◽  
Jin Cui ◽  
Zhi Qiang Liu
Keyword(s):  
Control System ◽  
High Voltage ◽  
Integrated Circuit ◽  
Design Automation ◽  
High Speed ◽  
Electrostatic Precipitator ◽  
Hardware Description Language ◽  
Description Language ◽  
Hardware Description ◽  
Very High

In order to achieve the automatic control of electrostatic precipitator (ESP) more efficiently and accurately, an ESP system combining hardware and software is designed. According to the requirement of the ESP system,the Electronic Design Automation (EDA) is introduced to the ESP control system and the system is divided into four modules.These sub-modules are designed and the simulation waveform of the system is ananalyzed,based on the Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) programming language and Quartus software.The results show that the security, flexibility and reliabity of the system is improved by using EDA as the control ,which is a great value for generalization.

Performance Analysis of an Area Efficient and Low Power MOD-R2MDC FFT for MIMO OFDM

2014 ◽  
Vol 573 ◽  
pp. 176-180
Author(s):  
G. Kavitha ◽  
B. Kirthiga ◽  
N. Kirubanandasarathy
Keyword(s):  
Low Power ◽  
Orthogonal Frequency Division Multiplexing ◽  
Ofdm System ◽  
Description Language ◽  
Fft Processor ◽  
Synthesis Tool ◽  
Mimo Ofdm ◽  
Hardware Description ◽  
Fft Algorithms ◽  
Area Efficient

In this paper, an area-efficient low power fast fourier transform (FFT) processor is proposed for multi input multi output-orthogonal frequency division multiplexing (MIMO-OFDM) in wireless communication system. It consists of a modified architecture of radix-2 algorithm which is described as modified radix-2 multipath delay commutation (MOD-R2MDC). The OFDM receiver with modified R2MDC (MOD-R2MDC) FFT was designed by Hardware Description Language (HDL) coding The Xilinx ISE Design Suite 10.1 is used as a synthesis tool for getting the power and area. The Model-Sim 6.3c is used for simulation. Also the existing OFDM system has been tested with these FFT algorithms and their performances were analyzed with respect to occupancy area in FPGA and power consumption. A low-power and area efficient architecture enables the real-time operations of MIMO OFDM system.

Serial-Communication between PLC and Host Computer in Spatial Carport

2012 ◽  
Vol 190-191 ◽  
pp. 168-172 ◽  
Author(s):  
Shu Leng Dong ◽  
Fang Wang ◽  
Jin Lan Yu
Keyword(s):  
Control System ◽  
Serial Communication ◽  
Communication Protocols ◽  
Visual Basic ◽  
Host Computer ◽  
Communication Program ◽  
Visual Basic 6.0

This paper describes the implementation of serial communication between the PLC and the host- computer in the control system of Spatial Carport, gives a detailed introduction to the communication protocols, parameters setting and also gives part of the serial-communication program based on visual basic 6.0. It shows that this control system meets the requirements as expected.

Hierarchical Configurable Petri Net Modeling in VHDL

2012 ◽  
Vol 58 (4) ◽  
pp. 397-402 ◽  
Author(s):  
Michał Doligalski ◽  
Marian Adamski
Keyword(s):  
Petri Nets ◽  
Petri Net ◽  
Control Process ◽  
Discrete Control ◽  
Dual Model ◽  
Description Language ◽  
Direct Support ◽  
Hardware Description ◽  
Logical Synthesis ◽  
State Machine Diagram

Abstract The paper presents method for hierarchical configurable Petri nets description in VHDL language. Dual model is an alternative way for behavioral description of the discrete control process. Dual model consists of two correlated models: UML state machine diagram and hierarchical configurable Petri net (HCfgPN). HCfgPN are Petri nets variant with direct support of exceptions handling mechanism. Logical synthesis of dual model is realized by the description of HCfgPN model by means of hardware description language. The paper presents placesoriented method for HCfgPN description in VHDL language

Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation

2017 ◽  
Vol 26 (09) ◽  
pp. 1750135 ◽  
Author(s):  
Ranjan Kumar Barik ◽  
Manoranjan Pradhan ◽  
Rutuparna Panda
Keyword(s):  
Final Stage ◽  
Hardware Description Language ◽  
Binary Representation ◽  
Description Language ◽  
Power Product ◽  
Efficient Conversion ◽  
Look Ahead ◽  
Hardware Description ◽  
Sign Extension ◽  
Cadence Tool

Redundant Binary (RB) to Two’s Complement (TC) converter offers nonredundant representation. However, the sign bit of TC representation has to be handled using nonstandard hardware blocks. The concept of Inverted encoding of negative weighted bits (IEN) eliminates the need of sign extension and offers design only using predefined hardware blocks. NonRedundant Binary (NRB) representation refers to both conventional and IEN representations. The NRB representation is also useful considering problem related to shifting in Carry Save (CS) representation of a RB number. In this paper, we have proposed two new conversion circuits for RB to NRB representation. The proposed circuits of the RB to NRB converter are coded in Verilog Hardware Description language (HDL) and synthesized using the Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 of Cadence tool considering ASIC platform. Considering 64 bits’ operand, the delay power product performances of proposed one-bit and two-bit computations offer improvement of almost 29.9% and 47%, respectively as compared to Carry-Look-Ahead (CLA). The proposed one-bit converter is also applied in the final stage of the Modified Redundant Binary Adder (MRBA). The 32-bit MRBA offers a delay improvement of 7.87% replacing conventional converter with proposed one-bit converter in same FPGA 4vfx12sf363-12 device.

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