logical state
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Author(s):  
Oksana O. Dakhova ◽  
Lyudmila L. Kairova ◽  
Buzigit M. Khuchunaev ◽  
Gennady V. Kupovykh

To map the territory of the Kabardino-Balkar Republic, long-term data on geoecological, geological, geochemical and hydrogeological characteristics of its state were collected, systematized and analyzed. On the basis of the per-formed geo-ecological testing, zoning of the territory of the Republic was carried out. The assessment of the geoeco-logical state of natural landscapes and the degree of anthropogenic impact is made. It is established that the problem of environmental pollution is becoming more and more urgent, both due to the growth of industrial and agricultural production, and due to its qualitative change under the influence of scientific and technological progress. It is shown that the main sources of technogenic pollution in the studied region are industrial enterprises, motor vehicles and utilities. Ecological zoning has been carried out in the territory of the KBR, and 11 areas that differ in the degree of ecological well-being have been identified and outlined on its basis.


Author(s):  
Michal Kelemen ◽  
Peter Ján Sinčák

Urgency of the research. Programmable logic controller are devices for controlling of various systems also in industry. If controlled device is complicated, it is problem to debug application, because of risk of its damage. For this purpose is better to use hardware training stand for testing of your designed application. Target setting. Training stand is as compact small device which is easy to move to another place. Also it allows to connect other hardware device for testing. Logical state hardware simulator is also designed for simulation of logic system with any user inputs with buttons or switches and also witch coloured lights for visualisation of output state.Actual scientific researches and issues analysis. Training set allows to make simulation of control system with real parts before its practical use with expensive controlled system, where any mistake can cause a huge economist loses, but errors occurred during the simulation on training set only make warning and shows the weak place on design. Uninvestigated parts of general matters defining. The questions of the networked structure of programmable logic controller structures are uninvestigated, so the next research will be focused to this. The research objective. The main goal is to create a compact device for training future application developers with a programmable logic controller, but it is also usable for developers from practice, who need to debug the program before installing it into real operation. The statement of basic materials. Existing training sets are large and expensive devices that are not easy to carry and cannot be expanded. Working with such devices is quite complicated. The designed training stand is a flexible and easily portable device. Conclusions. Main contribution is that students will gain practical experiences and skills that are essential for PLC programmers. This device supports also own creativity of students, because it allows to modify hardware composition. It uses the DIN rail system similar as in real installation cabinet. The stand also includes the human-machine interface for training of practical using of these devices.


2020 ◽  
Vol 4 (8) ◽  
pp. 73-84
Author(s):  
Mykhailo Tyhanskyi ◽  
Andrii Partyka

The goal of this work is to find ways of enhancing the speed of computer memory cells by using structures that employ operating principles other than those of traditional semiconductors’ schemes. One of the applications of the unique properties of Josephson structures is their usage in novel superfast computer memory cells. Thanks to their high working characteristic frequencies close to 1 THz, the Josephson structures are most promising candidates to be used in petaflop computers. Moreover, both Josephson cryotrons and Josephson SQUIDs can be used in qubits, which are basic units in quantum computers, and also for describing a macroscopic quantum behavior, for example, during read-out processes in quantum computations. In the present work, we have created a mathematical model of transition processes in Josephson cryotrons during direct, “1” → ”0”, as well as inverse, “0” → “1”, logical transitions. We have considered controlling the logical state of Josephson memory cells based on Josephson tunneling junctions of the S-I-S type via external current pulses. By means of mathematical modelling, we have studied transition processes in cryotrons during the change of their logical state and calculated their transition characteristics for working temperatures T1 = 11.6 K and T2 = 81.2 K, which ale close to the boiling temperatures of helium and nitrogen, respectively. It has been shown that such memory cells can effectively operate at the working temperature T2 = 81.2 K. We have determined commutation times for both the direct “0” → “1” and inverse “0” → “1” transitions. We have also identified peculiar behaviors of the Josephson cryotrons based memory cells and studied the stability of their operation.


Author(s):  
Mariana Natalia Ibarra-Bonilla ◽  
Fernando Sánchez-Texis ◽  
Raúl Eusebio-Grande ◽  
Fernando Julián Quiñones-Novelo

A hexapod robot control system hardware architecture is presented. The control system is integrated in an FPGA XC6SLX16-Spartan6. The design is developed using hardware description language, VHDL. A robust architecture, divided into three logical state machine blocks, is implemented in the FPGA. Block one consists of a serial communication system for the information interchange between the user and the FPGA. The second block corresponds to the sequential circuit and data manager in charge of controlling the functions of the entire architecture. The third block is an 18-channel PWM pulse generator with a progressive duty cycle change control to perform robot movements. The system is designed to allow the user to download a complex movements sequence by combining different positions and waiting times. The architecture allows to save up to 10 movements different sequences in the internal memory block. Additionally, it allows modifying any sequence in real time, without affecting the robot operation. The architecture controls 18 servomotors allowing 18 degrees of freedom to the robot. The performing and movement test of the robot are presented.


Quantum ◽  
2019 ◽  
Vol 3 ◽  
pp. 120 ◽  
Author(s):  
Tomas Jochym-O'Connor

A method for the implementation of a universal set of fault-tolerant logical gates is presented using homological product codes. In particular, it is shown that one can fault-tolerantly map between different encoded representations of a given logical state, enabling the application of different classes of transversal gates belonging to the underlying quantum codes. This allows for the circumvention of no-go results pertaining to universal sets of transversal gates and provides a general scheme for fault-tolerant computation while keeping the stabilizer generators of the code sparse.


Author(s):  
Tyhanskyi Mykhailo ◽  
Partyka Andrii ◽  
Krysko Rostyslaw

Using of traditional logic elements in digital electronics has ensured the development of a wide range of electronic devices for many years. In parallel, research and development of logical elements are carried out on the basis of other non-traditional physical phenomena or effects, in particular logic elements based on the phenomenon of superconductivity, the prospect of which is the use of very small energy consumption and ultrahigh performance. For superconducting logic elements, using various Josephson cryoelectronic structures, known as Josephson cryotrons, based on the stationary and non-stationary effects of Josephson. On the basis of the Josephson cryotrons, one can create Josephson elements of computer memory, and Josephson elements of digital logic. The main requirements for the Josephson cryotrons are a stable operating mode and high speed or short switching time. Information about the mode of operation and the speed give us the transition characteristics of the cryotrons - the time dependence of the voltage on the cryotron while changing its logical state, which can be obtained either experimentally, or theoretically. This work aims at a search for new ways of increasing the switching rate of digital logical operators by employing physical structures other than the traditional semiconductor-based schemes. We propose the principles of designing digital logical operators based on Josephson cryotrons, whose operation utilizes the stationary and dynamical Josephson effects, and describe the operational principles of the logical elements “AND” and “OR” bases on tunneling Josephson junctions “superconductor-insulator-superconductor”. Our proposed mathematical models for the commutation processes in such logical elements allowed us to calculate their transition characteristics during the switching and to determine the main parameters in such models. It was shown that the logical elements “AND” and “OR” can be implemented on individual cryotrons and that their logical state can be controlled by input signals in a form of current pulses. Such logical elements meet all the requirements for digital logical elements and have switching time of about 2-3 ps, which indicates their significantly increased switching rate.


2012 ◽  
Vol 614-615 ◽  
pp. 1724-1728
Author(s):  
Ying Han ◽  
Long Hua Mu ◽  
Wei Zhuang

For the increasing development of smart grid and the basic requirements of smart substations for digital information, networked communication platform and standardized information sharing, it’s very necessary to do research on the merging unit, which is the important equipment in process layer of substations. In order to adapt to the development of smart substations, according to IEC61850-9-2 standards, a new merging unit based on dsPIC30F6014 and STM32F107 is designed in this paper and each function module is designed and analyzed. DsPIC is responsible for data receiving and processing and the controlling of logical state. STM32F107 is responsible for the synchronization of merging unit and Ethernet communication. Time-synchronization based on IEEE1588 precision time protocol is especially introduced in this paper.


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