scholarly journals Experimental studies and a double gate JFET model for analog integrated circuits

Doklady BGUIR ◽  
2021 ◽  
Vol 19 (7) ◽  
pp. 5-12
Author(s):  
Y. D. Galkin ◽  
O. V. Dvornikov ◽  
V. A. Tchekhovski ◽  
N. N. Prokopenko

One of directions of improving parameters of analog integrated circuits is a development of new and modernization of existing designs of integrated elements without significantly changing of a technological route of integrated circuit manufacturing with a simultaneous creation of new integrated elements models. The article considers the results of experimental studies of the double gate junction field-effect transistor manufactured according to the 3CBiT technological route of JSC Integral. Based on the obtained results, the electrical model of double gate junction field-effect transistor is proposed, which describes the features of its application in analog integrated circuits. Comparison of I-V characteristics of measurements results and created model simulation are presented. A small capacity and a reverse current of a double gate junction field-effect transistor top gate, an ability to compensate for the DC (direct current) component of an input current provide a significant improvement in the characteristics of analog integrated circuits such as electrometric operational amplifiers and charge-sensitive amplifiers. The developed double gate junction field-effect transistor can be used in signal readout devices required in the analog interfaces of space instrument sensors and nuclear electronics.

2010 ◽  
Vol 645-648 ◽  
pp. 1115-1118 ◽  
Author(s):  
Xiao An Fu ◽  
Amita Patil ◽  
Te Hao Lee ◽  
Steven Garverick ◽  
Mehran Mehregany

We report fabrication of lateral, n-channel, depletion-mode, junction-field-effect-transistor (JFET) monolithic analog integrated circuits (ICs) in 6H-SiC. Ti/TaSi2/Pt forms the contact metalization, Ti/Pt the interconnect metal, and the SiO2/Si3N4/SiO2 interlayer dielectric. The threshold voltage and pinch off current indicate that the actual channel doping and thickness is close to the nominal values specified. The wafer yield for good circuits of a single-stage differential amplifier is 54% out of 46 copies.


2021 ◽  
Vol 16 (1) ◽  
Author(s):  
Xiaoshi Jin ◽  
Yicheng Wang ◽  
Kailu Ma ◽  
Meile Wu ◽  
Xi Liu ◽  
...  

AbstractA bilateral gate-controlled S/D symmetric and interchangeable bidirectional tunnel field effect transistor (B-TFET) is proposed in this paper, which shows the advantage of bidirectional switching characteristics and compatibility with CMOS integrated circuits compared to the conventional asymmetrical TFET. The effects of the structural parameters, e.g., the doping concentrations of the N+ region and P+ region, length of the N+ region and length of the intrinsic region, on the device performances, e.g., the transfer characteristics, Ion–Ioff ratio and subthreshold swing, and the internal mechanism are discussed and explained in detail.


Nano Letters ◽  
2010 ◽  
Vol 10 (8) ◽  
pp. 2934-2938 ◽  
Author(s):  
Jae-Hyuk Ahn ◽  
Sung-Jin Choi ◽  
Jin-Woo Han ◽  
Tae Jung Park ◽  
Sang Yup Lee ◽  
...  

2021 ◽  
Author(s):  
Dharmender Nishad ◽  
Kaushal Nigam ◽  
Satyendra Kumar

Abstract Temperature-induced performance variation is one of the main concerns of the conventional stack gate oxide double gate tunnel field-effect transistor (SGO-DG-TFET). In this regard, we investigate the temperature sensitivity of extended source double gate tunnel field-effect transistor (ESDG-TFET). For this, we have analyzed the effect of temperature variations on the transfer characteristics, analog/RF, linearity and distortion figure of merits (FOMs) using technology computer aided design (TCAD) simulations. Further, the temperature sensitivity performance is compared with conventional SGO-DG-TFET. The comparative analysis shows that ESDG-TFET is less sensitive to temperature variations compared to the conventional SGO-DG-TFET. Therefore, this indicates that ESDG-TFET is more reliable for low-power, high-frequency applications at a higher temperature compared to conventional SGO-DG-TFET.


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