Fabrication of SiC JFET-Based Monolithic Integrated Circuits

2010 ◽  
Vol 645-648 ◽  
pp. 1115-1118 ◽  
Author(s):  
Xiao An Fu ◽  
Amita Patil ◽  
Te Hao Lee ◽  
Steven Garverick ◽  
Mehran Mehregany
Keyword(s):  
Integrated Circuits ◽  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Analog Integrated Circuits ◽  
Single Stage ◽  
Differential Amplifier ◽  
Interlayer Dielectric ◽  
Monolithic Integrated Circuits ◽  
Effect Transistor

We report fabrication of lateral, n-channel, depletion-mode, junction-field-effect-transistor (JFET) monolithic analog integrated circuits (ICs) in 6H-SiC. Ti/TaSi2/Pt forms the contact metalization, Ti/Pt the interconnect metal, and the SiO2/Si3N4/SiO2 interlayer dielectric. The threshold voltage and pinch off current indicate that the actual channel doping and thickness is close to the nominal values specified. The wafer yield for good circuits of a single-stage differential amplifier is 54% out of 46 copies.

scholarly journals Experimental studies and a double gate JFET model for analog integrated circuits

Doklady BGUIR ◽  
2021 ◽  
Vol 19 (7) ◽  
pp. 5-12
Author(s):  
Y. D. Galkin ◽  
O. V. Dvornikov ◽  
V. A. Tchekhovski ◽  
N. N. Prokopenko
Keyword(s):  
Integrated Circuits ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Model Simulation ◽  
Experimental Studies ◽  
Reverse Current ◽  
Analog Integrated Circuits ◽  
Double Gate ◽  
Effect Transistor ◽  
Technological Route

One of directions of improving parameters of analog integrated circuits is a development of new and modernization of existing designs of integrated elements without significantly changing of a technological route of integrated circuit manufacturing with a simultaneous creation of new integrated elements models. The article considers the results of experimental studies of the double gate junction field-effect transistor manufactured according to the 3CBiT technological route of JSC Integral. Based on the obtained results, the electrical model of double gate junction field-effect transistor is proposed, which describes the features of its application in analog integrated circuits. Comparison of I-V characteristics of measurements results and created model simulation are presented. A small capacity and a reverse current of a double gate junction field-effect transistor top gate, an ability to compensate for the DC (direct current) component of an input current provide a significant improvement in the characteristics of analog integrated circuits such as electrometric operational amplifiers and charge-sensitive amplifiers. The developed double gate junction field-effect transistor can be used in signal readout devices required in the analog interfaces of space instrument sensors and nuclear electronics.

scholarly journals A Study on the Effect of the Structural Parameters and Internal Mechanism of a Bilateral Gate-Controlled S/D Symmetric and Interchangeable Bidirectional Tunnel Field Effect Transistor

2021 ◽  
Vol 16 (1) ◽  
Author(s):  
Xiaoshi Jin ◽  
Yicheng Wang ◽  
Kailu Ma ◽  
Meile Wu ◽  
Xi Liu ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Structural Parameters ◽  
Cmos Integrated Circuits ◽  
Region Length ◽  
Internal Mechanism ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Switching Characteristics

AbstractA bilateral gate-controlled S/D symmetric and interchangeable bidirectional tunnel field effect transistor (B-TFET) is proposed in this paper, which shows the advantage of bidirectional switching characteristics and compatibility with CMOS integrated circuits compared to the conventional asymmetrical TFET. The effects of the structural parameters, e.g., the doping concentrations of the N+ region and P+ region, length of the N+ region and length of the intrinsic region, on the device performances, e.g., the transfer characteristics, Ion–Ioff ratio and subthreshold swing, and the internal mechanism are discussed and explained in detail.

scholarly journals Silicon Field Effect Transistor as the Nonlinear Detector for Terahertz Autocorellators

Sensors ◽  
2018 ◽  
Vol 18 (11) ◽  
pp. 3735 ◽  
Author(s):  
Kęstutis Ikamas ◽  
Ignas Nevinskas ◽  
Arūnas Krotkus ◽  
Alvydas Lisauskas
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Cryogenic Cooling ◽  
Thz Radiation ◽  
Gate Bias ◽  
Large Signal ◽  
Wide Range ◽  
Effect Transistor ◽  
Thz Power

We demonstrate that the rectifying field effect transistor, biased to the subthreshold regime, in a large signal regime exhibits a super-linear response to the incident terahertz (THz) power. This phenomenon can be exploited in a variety of experiments which exploit a nonlinear response, such as nonlinear autocorrelation measurements, for direct assessment of intrinsic response time using a pump-probe configuration or for indirect calibration of the oscillating voltage amplitude, which is delivered to the device. For these purposes, we employ a broadband bow-tie antenna coupled Si CMOS field-effect-transistor-based THz detector (TeraFET) in a nonlinear autocorrelation experiment performed with picoseconds-scale pulsed THz radiation. We have found that, in a wide range of gate bias (above the threshold voltage V th = 445 mV), the detected signal follows linearly to the emitted THz power. For gate bias below the threshold voltage (at 350 mV and below), the detected signal increases in a super-linear manner. A combination of these response regimes allows for performing nonlinear autocorrelation measurements with a single device and avoiding cryogenic cooling.

scholarly journals An Improved UU-MESFET with High Power Added Efficiency

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 573 ◽  
Author(s):  
Hujun Jia ◽  
Mei Hu ◽  
Shunwei Zhu
Keyword(s):  
Breakdown Voltage ◽  
Threshold Voltage ◽  
High Power ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Drain Current ◽  
Power Added Efficiency ◽  
Effect Transistor ◽  
The Relationship

An improved ultrahigh upper gate 4H-SiC metal semiconductor field effect transistor (IUU-MESFET) is proposed in this paper. The structure is obtained by modifying the ultrahigh upper gate height h of the ultrahigh upper gate 4H-SiC metal semiconductor field effect transistor (UU-MESFET) structure, and the h is 0.1 μm and 0.2 μm for the IUU-MESFET and UU-MESFET, respectively. Compared with the UU-MESFET, the IUU-MESFET structure has a greater threshold voltage and trans-conductance, and smaller breakdown voltage and saturation drain current, and when the ultrahigh upper gate height h is 0.1 μm, the relationship between these parameters is balanced, so as to solve the contradictory relationship that these parameters cannot be improved simultaneously. Therefore, the power added efficiency (PAE) of the IUU-MESFET structure is increased from 60.16% to 70.99% compared with the UU-MESFET, and advanced by 18%.

scholarly journals The impact of channel fin width on electrical characteristics of Si-FinFET

2022 ◽  
Vol 12 (1) ◽  
pp. 201
Author(s):  
Yousif Atalla ◽  
Yasir Hashim ◽  
Abdul Nasir Abd. Ghafar
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Environmental Temperature ◽  
Simulation Tool ◽  
Electrical Characteristics ◽  
Working Temperature ◽  
Effect Transistor ◽  
The Impact ◽  
The Ideal

<span>This paper studies the impact of fin width of channel on temperature and electrical characteristics of fin field-effect transistor (FinFET). The simulation tool multi-gate field effect transistor (MuGFET) has been used to examine the FinFET characteristics. Transfer characteristics with various temperatures and channel fin width (W<sub>F</sub>=5, 10, 20, 40, and 80 nm) are at first simulated in this study. The results show that the increasing of environmental temperature tends to increase threshold voltage, while the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) rise with rising working temperature. Also, the threshold voltage decreases with increasing channel fin width of transistor, while the SS and DIBL increase with increasing channel fin width of transistor, at minimum channel fin width, the SS is very near to the best and ideal then its value grows and going far from the ideal value with increasing channel fin width. So, according to these conditions, the minimum value as possible of fin width is the preferable one for FinFET with better electrical characteristics.</span>

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