A robust single device MOSFET series resistance extraction method considering horizontal-field-dependent mobility

Author(s):  
Kiyoshi Takeuchi ◽  
Tomoko Mizutani ◽  
Takuya Saraya ◽  
Masaharu Kobayashi ◽  
Toshiro HIRAMOTO

Abstract A simple MOSFET series resistance extraction method using multiple drain current vs. gate voltage curves of a single device is proposed, where mobility modulation by horizontal electric field (i.e., weak velocity saturation) is taken into account. The method is validated using TCAD, where series resistance determined from internal potential distributions was used as reliable reference. Measurement results were also obtained which further support the validity of the method.

Author(s):  
Xinhua Wang ◽  
Yuanqi Jiang ◽  
Sen Huang ◽  
Yingkui Zheng ◽  
Ke Wei ◽  
...  

Electronics ◽  
2020 ◽  
Vol 10 (1) ◽  
pp. 63
Author(s):  
Saima Hasan ◽  
Abbas Z. Kouzani ◽  
M A Parvez Mahmud

This paper presents a simple and comprehensive model of a dual-gate graphene field effect transistor (FET). The quantum capacitance and surface potential dependence on the top-gate-to-source voltage were studied for monolayer and bilayer graphene channel by using equivalent circuit modeling. Additionally, the closed-form analytical equations for the drain current and drain-to-source voltage dependence on the drain current were investigated. The distribution of drain current with voltages in three regions (triode, unipolar saturation, and ambipolar) was plotted. The modeling results exhibited better output characteristics, transfer function, and transconductance behavior for GFET compared to FETs. The transconductance estimation as a function of gate voltage for different drain-to-source voltages depicted a proportional relationship; however, with the increase of gate voltage this value tended to decline. In the case of transit frequency response, a decrease in channel length resulted in an increase in transit frequency. The threshold voltage dependence on back-gate-source voltage for different dielectrics demonstrated an inverse relationship between the two. The analytical expressions and their implementation through graphical representation for a bilayer graphene channel will be extended to a multilayer channel in the future to improve the device performance.


2021 ◽  
Vol 104 (5) ◽  
Author(s):  
Guangxiu Liu ◽  
Zhehong Liu ◽  
Yisheng Chai ◽  
Long Zhou ◽  
Xudong Shen ◽  
...  

2010 ◽  
Vol 108 (1) ◽  
pp. 014512 ◽  
Author(s):  
Michele Giulianini ◽  
Eric R. Waclawik ◽  
John M. Bell ◽  
Nunzio Motta

1991 ◽  
Vol 30 (Part 2, No. 4A) ◽  
pp. L612-L615 ◽  
Author(s):  
Ying-Bao Yang ◽  
Akihiro Mochizuki ◽  
Naoto Nakamura ◽  
Shunsuke Kobayashi

1973 ◽  
Vol 13 (10) ◽  
pp. 1721-1724 ◽  
Author(s):  
W.R. Salaneck ◽  
J.S. Berkes

2021 ◽  
Vol 11 (5) ◽  
pp. 2210
Author(s):  
Bartosz Lasek ◽  
Przemysław Trochimiuk ◽  
Rafał Kopacz ◽  
Jacek Rąbkowski

This article discusses an active gate driver for a 1.7 kV/325 A SiC MOSFET module. The main purpose of the driver is to adjust the gate voltage in specified moments to speed up the turn-on cycle and reduce the amount of dissipated energy. Moreover, an adequate manipulation of the gate voltage is necessary as the gate current should be reduced during the rise of the drain current to avoid overshoots and oscillations. The gate voltage is switched at the right moments on the basis of the feedback signal provided from a measurement of the voltage across the parasitic source inductance of the module. This approach simplifies the circuit and provides no additional power losses in the measuring circuit. The paper contains the theoretical background and detailed description of the active gate driver design. The model of the parasitic-based active gate driver was verified using the double-pulse procedure both in Saber simulations and laboratory experiments. The active gate driver decreases the turn-on energy of a 1.7 kV/325 A SiC MOSFET by 7% comparing to a conventional gate driver (VDS = 900 V, ID = 270 A, RG = 20 Ω). Furthermore, the proposed active gate driver lowered the turn-on cycle time from 478 to 390 ns without any serious oscillations in the main circuit.


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