scholarly journals Transistor sizing of CMOS VLSI Circuits in Deep Submicron Technology

2019 ◽  
Vol 8 (11S2) ◽  
pp. 15-29
Keyword(s):  
Full Adder ◽  
Deep Submicron ◽  
Vlsi Circuits ◽  
Total Power ◽  
Cmos Inverter ◽  
Transistor Sizing ◽  
Cmos Vlsi

In Very-huge scale reconciliation (VLSI) application zone, postponement and power are the significant variables for any advanced circuits. Its observed that the as CMOS Inverter Transistor Size decreases from 1µm to 120nm, power reduced from 3.331 to 2.644 (µW) and delay reduced from 5.026 to 22.66 (pS). It is observed that the table 4 as 28T Full Adder Circuit Voltage Scale decreases from 5 V to 1 V, Total power reduced from 63150 to 2262 (nW) and delay reduced from 39.93 to 38.52 (nS) in 180nm technology. It is observed that the table 6 as 28T Full Adder Circuit Voltage Scale decreases from 2 V to 0.8 V, Total power reduced from 21.39 to 2.916 (µW) and delay reduced from 4.939 to 4.74 (nS) in 90nm technology. It is observed that the table 8 as 28T Full Adder Circuit Voltage Scale decreases from 1.5 V to 0.7 V, Total power reduced from 8.98 to 1.713 (µW) and delay reduced from 4.963 to 4.581 (nS) in 45nm technology.

scholarly journals An Efficient Power Optimized 32 bit BCD Adder Using Multi-Channel Technique

2017 ◽  
Vol 6 (02) ◽  
pp. 07-12
Author(s):  
Diksha Siddhamshittiwar
Keyword(s):  
Average Power ◽  
Full Adder ◽  
Deep Submicron ◽  
Power Reduction ◽  
Vlsi Circuits ◽  
Power Gating ◽  
Static Power ◽  
Simulation Results ◽  
Efficient Power ◽  
Standby Mode

Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

Adaptive Thermal Monitoring of Deep-Submicron CMOS VLSI Circuits

2013 ◽  
Vol 9 (4) ◽  
pp. 403-413
Author(s):  
Amir Zjajo ◽  
Nick van der Meijs ◽  
Rene van Leuken
Keyword(s):  
Deep Submicron ◽  
Vlsi Circuits ◽  
Thermal Monitoring ◽  
Submicron Cmos ◽  
Cmos Vlsi

scholarly journals IMPLEMENTATION OF ELECTRONIC DEVICES OF CMOS FULL ADDER IN LOW POWER VLSI CIRCUITS

2021 ◽  
Vol 2089 (1) ◽  
pp. 012081
Author(s):  
P. Durgaprasadarao ◽  
K.V. Daya Sagar
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Electricity Consumption ◽  
Basic Feature ◽  
Full Adder ◽  
Vlsi Circuits ◽  
Total Power ◽  
Electronic Systems ◽  
Power Characteristics ◽  
Total Power Consumption

Abstract Battery-powered devices (for example, mobile phones, digital personal aids, etc) are increasing on the mobile electronic systems market by developing microelectronic circuits with low energy dissipation. The problem of dissipating power could limit the flexibility of the computer system, as the chip’s density and complexity keep on increasing. The power supply consumes approximately 35% of the chip power, particularly at the nanometer level. The purpose of this project is to investigate the efficiency of one of the most reliable low power concepts called Power Gating. It is only nanometer-scale CMOS devices that are the most common technology in existing VLSI systems. Leakage power has become an integral component of total power in the nanometer technology regime. The ALU’s basic feature unit is Full Adder. The electricity consumption of an ALU is decreased by decreasing the energy consumption of an ALU, and an ALU will reduce the power consumption by decreasing the total power consumption. So these days, the complete adder designs are becoming more common with low power characteristics. The proposed project shows the concept of the micro wind tool for low power less transistors.

Reliability-Driven CAD System for Deep-Submicron VLSI Circuits

1998 ◽  
Author(s):  
S. M. Kang ◽  
E. Rosenbaum ◽  
Y. K. Cheng ◽  
L. P. Yuan ◽  
T. Li
Keyword(s):  
Deep Submicron ◽  
Vlsi Circuits ◽  
Cad System
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