scholarly journals Design and Development of a Modified AXI Based BIST Technique for Memory Architectures

2019 ◽  
Vol 8 (4) ◽  
pp. 8023-8029
Keyword(s):  
Fault Detection ◽  
Random Access ◽  
Memory Systems ◽  
Memory Architecture ◽  
Proposed Model ◽  
Overall Performance ◽  
Self Test ◽  
On Chip ◽  
The Cost ◽  
Memory Architectures

Memory testing and fault detection is an important phase in testing the hardware devices. This improves the overall performance of the system and prevents runtime failures in the devices. Built In Self Test (BIST) is a hardware memory test architecture deployed in many System on Chip devices to enable fault detection. This technique reduces the cost and time needed to test the memory systems. Different BIST modules need to be used to detect faults in different memories. As a result, design complexity increases. In order to overcome these above shortcomings, it is essential to develop advanced extensible Interface (AXI) with Block Random Access Memory (BRAM) and Design and Develop AXI based self-test memory architecture (March Algorithms) to achieve parallel read and write capability. The proposed model reduced the dynamic power and the clock cycles needed for simulation when compared to existing techniques

Design and Simulation of Bipolar 4H-SiC Memory Architecture for High Temperature Applications

2018 ◽  
Vol 924 ◽  
pp. 953-957
Author(s):  
Hazem Elgabra ◽  
Amna Siddiqui ◽  
Shakti Singh
Keyword(s):  
Supply Voltage ◽  
Random Access ◽  
Memory Cell ◽  
Electronic System ◽  
Small Scale ◽  
Stable Operation ◽  
Memory Architecture ◽  
Wide Range ◽  
Increasing Demand ◽  
Memory Architectures

The increasing demand for electronics in harsh environment applications has inspired investigation of silicon carbide (SiC)-based devices and circuits, due to its superior electrical properties. Several researchers have demonstrated the viability of 4H-SiC control circuitry by developing small scale logic circuits entirely in 4H-SiC. However, development and design of memory elements, which is a critical component in any electronic system, is still not fully explored. To bridge this gap, this paper presents, a complete bipolar, static random access memory (SRAM) column that includes the memory cell and the peripheral circuitry, designed to exploit the unique properties of SiC. Simulation results for the proposed memory show stable operation across a wide range of temperatures (27 °C – 500 °C) with good noise margins and access speeds while running at a supply voltage as low as 5 V. This work validates the potential of developing memory architectures in 4H-SiC, paving the way for realizing small-sized digital systems for harsh environments.

scholarly journals Optimal Alternatives by Controlling Time and Cost of a Multi-Level Car Park Using Excel-Solver Program

2019 ◽  
Vol 54 (6) ◽  
Author(s):  
Sada Abdalkhaliq Hasan
Keyword(s):  
Optimal Solution ◽  
Time Frame ◽  
Proposed Model ◽  
Car Park ◽  
Overall Performance ◽  
Multi Level ◽  
Excel Solver ◽  
The Cost ◽  
The City

In this research the best cost and time are identified to implement a multi-level car park. The aim of this research is to develop a time frame model, including time and cost analysis, and to find optimal alternatives for a multi-level garage project during the planning phase. The proposed model has been developed using Solver program in Excel built for combining cost and time calculations by adopting the Project Management Software (MS-Project) to facilitate optimal solution access. In future the same project can be implemented at the lowest possible cost. This research concluded that it is possible to obtain the optimal solution after analyzing the alternatives using the Solver program and then taking the results of the optimization process to perform the improvement of the timeline. The research highlights the factors such as: the estimated cost, the planned time and the alternatives available for optimum performance aimed at finding optimal solutions and thus enhancing overall performance. The research was applied to the case study of one of the projects implemented within the city and found that the results are consistent with the research objective. According application of the model, the solution shows it will reduce cost and time to about 190292 $ and 91day from the cost and time of actual project.

scholarly journals Polymorphic Memory: A Hybrid Approach for Utilizing On-Chip Memory in Manycore Systems

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2061
Author(s):  
Seung-Ho Lim ◽  
Hyunchul Seok ◽  
Ki-Woong Park
Keyword(s):  
High Performance ◽  
Hybrid Approach ◽  
Random Access ◽  
Previous Method ◽  
Main Memory ◽  
Memory Architecture ◽  
Memory Hierarchies ◽  
Dynamic Memory ◽  
High Bandwidth ◽  
On Chip

The key challenges of manycore systems are the large amount of memory and high bandwidth required to run many applications. Three-dimesnional integrated on-chip memory is a promising candidate for addressing these challenges. The advent of on-chip memory has provided new opportunities to rethink traditional memory hierarchies and their management. In this study, we propose a polymorphic memory as a hybrid approach when using on-chip memory. In contrast to previous studies, we use the on-chip memory as both a main memory (called M1 memory) and a Dynamic Random Access Memory (DRAM) cache (called M2 cache). The main memory consists of M1 memory and a conventional DRAM memory called M2 memory. To achieve high performance when running many applications on this memory architecture, we propose management techniques for the main memory with M1 and M2 memories and for polymorphic memory with dynamic memory allocations for many applications in a manycore system. The first technique is to move frequently accessed pages to M1 memory via hardware monitoring in a memory controller. The second is M1 memory partitioning to mitigate contention problems among many processes. Finally, we propose a method to use M2 cache between a conventional last-level cache and M2 memory, and we determine the best cache size for improving the performance with polymorphic memory. The proposed schemes are evaluated with the SPEC CPU2006 benchmark, and the experimental results show that the proposed approaches can improve the performance under various workloads of the benchmark. The performance evaluation confirms that the average performance improvement of polymorphic memory is 21.7%, with 0.026 standard deviation for the normalized results, compared to the previous method of using on-chip memory as a last-level cache.

ON THE PERFORMANCE AND COST OF SOME PRAM MODELS ON CMP HARDWARE

2010 ◽  
Vol 21 (03) ◽  
pp. 387-404 ◽  
Author(s):  
MARTTI FORSELL
Keyword(s):  
Random Access ◽  
Chip Multiprocessor ◽  
Pram Model ◽  
Vlsi Technology ◽  
Cost Efficient ◽  
Performance Area ◽  
And Performance ◽  
On Chip ◽  
Parallel Random Access Machine ◽  
The Cost

The Parallel Random Access Machine is a very strong model of parallel computing that has resisted cost-efficient implementation attempts for decades. Recently, the development of VLSI technology has provided means for indirect on-chip implementation, but there are different variants of the PRAM model that provide different performance, area and power figures and it is not known how their implementations compare to each others. In this paper we measure the performance and estimate the cost of practical implementations of four PRAM models including EREW, Limited Arbitrary CRCW, Full Arbitrary CRCW, Full Arbitrary Multioperation CRCW on our Eclipse chip multiprocessor framework. Interestingly, the most powerful model shows the lowest simulation cost and highest performance/area and performance/power figures.

Effective Memory Architectures of Multi-Processor Systems-on-Chip

2010 ◽  
Vol 3 (3) ◽  
pp. 218-231
Author(s):  
Ni Zhou ◽  
Fei Qiao ◽  
Huazhong Yang ◽  
Hui Wang
Keyword(s):  
Systems On Chip ◽  
On Chip ◽  
Memory Architectures

scholarly journals An Optimized Mathematical Model for Items Supplies Planning of a Logistic System

2016 ◽  
Vol 10 (10) ◽  
pp. 133
Author(s):  
Mohammad Ali Nasiri Khalili ◽  
Mostafa Kafaei Razavi ◽  
Morteza Kafaee Razavi
Keyword(s):  
Mathematical Model ◽  
Mixed Integer ◽  
Logistics System ◽  
Proposed Model ◽  
Multiple Objective Decision Making ◽  
System Requirements ◽  
Purchasing Logistics ◽  
The Cost ◽  
The Mathematical Model ◽  
First Time

Items supplies planning of a logistic system is one of the major issue in operations research. In this article the aim is to determine how much of each item per month from each supplier logistics system requirements must be provided. To do this, a novel multi objective mixed integer programming mathematical model is offered for the first time. Since in logistics system, delivery on time is very important, the first objective is minimization of time in delivery on time costs (including lack and maintenance costs) and the cost of purchasing logistics system. The second objective function is minimization of the transportation supplier costs. Solving the mathematical model shows how to use the Multiple Objective Decision Making (MODM) can provide the ensuring policy and transportation logistics needed items. This model is solved with CPLEX and computational results show the effectiveness of the proposed model.

scholarly journals Demonstration of an integrated nanophotonic chip-scale alkali vapor magnetometer using inverse design

2021 ◽  
Vol 10 (1) ◽  
Author(s):  
Yoel Sebbag ◽  
Eliran Talker ◽  
Alex Naiman ◽  
Yefim Barash ◽  
Uriel Levy
Keyword(s):  
Spatial Resolution ◽  
Near Field ◽  
Computer Assisted ◽  
Experimental Characterization ◽  
Optical Isolation ◽  
New Concepts ◽  
On Chip ◽  
The Cost ◽  
Micrometer Scale

AbstractRecently, there has been growing interest in the miniaturization and integration of atomic-based quantum technologies. In addition to the obvious advantages brought by such integration in facilitating mass production, reducing the footprint, and reducing the cost, the flexibility offered by on-chip integration enables the development of new concepts and capabilities. In particular, recent advanced techniques based on computer-assisted optimization algorithms enable the development of newly engineered photonic structures with unconventional functionalities. Taking this concept further, we hereby demonstrate the design, fabrication, and experimental characterization of an integrated nanophotonic-atomic chip magnetometer based on alkali vapor with a micrometer-scale spatial resolution and a magnetic sensitivity of 700 pT/√Hz. The presented platform paves the way for future applications using integrated photonic–atomic chips, including high-spatial-resolution magnetometry, near-field vectorial imaging, magnetically induced switching, and optical isolation.

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