scholarly journals New 2 2 Sigma Delta Modulators for Different Applications

2021 ◽  
Vol 10 (4) ◽  
pp. 269-272
Author(s):  
Slim Tahri ◽  
◽  
Nizar Khitouni ◽  
Med Salim Bouhlel ◽  
◽  
...  
Keyword(s):  
Low Voltage ◽  
Signal To Noise Ratio ◽  
System Optimization ◽  
Quantization Noise ◽  
Pass Band ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Σδ Modulator ◽  
High Level ◽  
High Pass

This work presents the design of a new 2-2 programmable sigma delta modulator architecture, for different applications, this transformation design of the ΣΔ modulator low-pass, band-pass and high-pass or vice versa with loopbacks addition, which improved the linearity of the converter and reduced the quantization noise. In this work, the MASH structure enables the implementation of stable and high-order modulator. This makes low voltage and low power applications ideal. The simulation result for sigma delta modulator for biomedical applications exhibit a signal to noise ratio is 95 dB @ 250Hz bandwidth and a 75dB @ 200KHz ,85dB @1MHz for pass band modulator. The SNR is about 70dB for 5MHz bandwidth and for high pass application. This tool will allow a development contribution and characterize a system optimization set from the start while remaining at a high level of design that is suitable for electronic systems and models VHDL-AMS, RF, Biomedical.

A High Performance Fourth-Order Single-Loop Sigma Delta Modulator Applied in Micro-Inertial Sensors

2012 ◽  
Vol 503 ◽  
pp. 303-307
Author(s):  
Peng Fei Wang ◽  
Yuan Yuan ◽  
Dong Bo Wang ◽  
Xiao Wei Liu ◽  
Jun'an Liu
Keyword(s):  
Fourth Order ◽  
High Performance ◽  
Inertial Sensors ◽  
Signal To Noise Ratio ◽  
System Level ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Analysis And Design ◽  
The Stability ◽  
Σδ Modulator

This paper presents a fourth-order sigma delta (ΣΔ)modulator applied in micro-inertial sensors. After a introduction of sigma-delta modulator and its application in micro-inertial sensors, the system-level analysis and design is given and the gain coefficients is calculated. By the use of root locus, the stability of high order ΣΔ modulator is analyzed and it is got the minimum value of quantizer gain k is 0.287. The simulation shows that the signal to noise ratio (SNR) is 121.6 dB and the effective number of bits (ENOB) is 19.91 bits. When input level is smaller than -6 dBFs, the quantizer and integrators would not be overload and work well.

A High-Performance Mash Fourth-Order Sigma-Delta Modulator

2012 ◽  
Vol 503 ◽  
pp. 207-210
Author(s):  
Wen Yan Liu ◽  
Bin Zhang ◽  
Long Chen ◽  
Chao Gao ◽  
Xiao Wei Liu
Keyword(s):  
Fourth Order ◽  
High Performance ◽  
System Stability ◽  
Quantization Noise ◽  
System Level ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
System Level Simulation ◽  
Sampling Ratio ◽  
Σδ Modulator

This paper reports on a system level design and analysis of a mash fourth-order sigma-delta (ΣΔ) modulator. Compared with a high-order single-loop ΣΔ modulator (ΣΔM), there’s no need to consider about the system stability of a mash ΣΔM, which has the advantages of better signal to quantization noise ratio (SQNR). System level simulation results indicate that the SQNR is 122.0 dB, and the effective number of bits (ENOB) is 19.97 bits when the over sampling ratio (OSR) is 128.

scholarly journals Chip Design of a Low-Voltage Wideband Continuous-Time Sigma-Delta Modulator with DWA Technology for WiMAX Applications

2011 ◽  
Vol 02 (03) ◽  
pp. 201-209 ◽  
Author(s):  
Jhin-Fang Huang ◽  
Yan-Cheng Lai ◽  
Wen-Cheng Lai ◽  
Ron-Yi Liu
Keyword(s):  
Continuous Time ◽  
Low Voltage ◽  
Chip Design ◽  
Sigma Delta Modulator ◽  
Sigma Delta

A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs

2019 ◽  
Vol 29 (07) ◽  
pp. 2050108
Author(s):  
Di Li ◽  
Chunlong Fei ◽  
Qidong Zhang ◽  
Yani Li ◽  
Yintang Yang
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Oxide Semiconductor ◽  
Quantization Noise ◽  
Cmos Process ◽  
Noise Shaping ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.

A High Bandwidth Sigma-Delta Modulator Applied in Micro-Gyroscope

2013 ◽  
Vol 562-565 ◽  
pp. 369-373 ◽  
Author(s):  
Qiang Fu ◽  
Wei Ping Chen ◽  
Song Chen ◽  
Peng Fei Wang ◽  
Xiao Wei Liu
Keyword(s):  
Signal To Noise Ratio ◽  
System Simulation ◽  
Sampling Frequency ◽  
Effective Number ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
High Bandwidth ◽  
Oversampling Ratio ◽  
Input Level

In this paper a fourth-order single-loop sigma-delta modulator applied in micro-gyroscope is designed. The modulator system chose the fully feedforword structure. The signal bandwidth is 200KHz, oversampling ratio is 64 and sampling frequency is 25.6MHz. By system simulation result in Matlab, the signal to noise ratio (SNR) is 92.3dB and effective number of bits (ENOB) is 15.03bits. The whole circuit of modulator is designed and simulated in Cadence Spectre. It is gotten that the SNR is 78.6dB and changes linearly with input level. When input level is bigger than -4dBFs, the modulator becomes overload.

VCO-BASED CONTINUOUS-TIME SIGMA DELTA ADC BASED ON A DUAL-VCO-QUANTIZER-LOOP STRUCTURE

2013 ◽  
Vol 22 (09) ◽  
pp. 1340013 ◽  
Author(s):  
Z. T. XU ◽  
X. L. ZHANG ◽  
J. Z. CHEN ◽  
S. G. HU ◽  
Q. YU ◽  
...  
Keyword(s):  
Continuous Time ◽  
Signal To Noise Ratio ◽  
Quantization Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Loop Structure ◽  
Signal To Noise ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Sigma Delta Adc

This paper explores a continuous time (CT) sigma delta (ΣΔ) analog-to-digital converter (ADC) based on a dual-voltage-controlled oscillator (VCO)-quantizer-loop structure. A third-order filter is adopted to reduce quantization noise and VCO nonlinearity. Even-order harmonics of VCO are significantly reduced by the proposed dual-VCO-quantizer-loop structure. The prototype with 10 MHz bandwidth and 400 MHz clock rate is designed using a 0.18 μm RF CMOS process. Simulation results show that the signal-to-noise ratio and signal-to-noise distortion ratio (SNDR) are 76.9 and 76 dB, respectively, consuming 37 mA at 1.8 V. The key module of the ADC, which is a 4-bit VCO-based quantizer, can convert the voltage signal into a frequency signal and quantize the corresponding frequency to thermometer codes at 400 MS/s.

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