scholarly journals Design and Implementation of Hybrid FIR Filters using Vedic Multiplier and Fast Adders

2019 ◽  
Vol 8 (4) ◽  
pp. 11849-11853
Keyword(s):  
High Speed ◽  
High Performance ◽  
Noise Suppression ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Vital Role ◽  
Finite Impulse Response Filters ◽  
Vedic Multiplier ◽  
Impulse Response Filters

FIR (Finite Impulse Response) filters play a significant role in the field of Digital Signal Processing (DSP) to eliminate noise suppression in Electro Cardio Graph (ECG), Imaging devices and the signal stored in analog media. So filter evaluation is accomplished to reduce the noise level. The Filter passes only the desired frequency to pass thereby reducing distortion in the processed signal during measurement. The FIR filter comprises of basic units like adders, multipliers and the delay element for its operations.FIR and IIR are the two types of digital filters chosen based on the range of inputs, complexity and size requirement. Multipliers and adders play a vital role in deterring the performance of FIR filter. In this work, we design and analyze different multiplier and adder for high-performance Fir filter implementation. The Vedic Mathematics is the methods containing 16 Sutras to aid fast mental calculations. In this work, we propose modified Anurupye Vedic multiplier methods with Kogge Stone fast adder for implementation in the direct form FIR filter. This approach provides 1.5% decrease in delay and 10.2% reduced in power, hence increasing speed marginally than previous methods. Along with low power consumption in Very High-Speed Hardware Description Language (VHDL), all the adders and the multiplier topologies are Synthesized using (Xilinx Spartan – 6 FPGA) Trainer Kit and the proposed 8 – Tap FIR filter is executed using this Board

scholarly journals DESIGN OF HIGH PERFORMANCE MULTIPLIERLESS LINEAR PHASE FINITE IMPULSE RESPONSE FILTERS

2017 ◽  
Vol 10 (13) ◽  
pp. 66
Author(s):  
A Aparna ◽  
T Vigneswaran
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
High Performance ◽  
Finite Impulse Response ◽  
Research Work ◽  
Digital Signal ◽  
Fir Filter ◽  
Pass Filter ◽  
Finite Impulse Response Filters

This research work proposes the finite impulse response (FIR) filters design using distributed arithmetic architecture optimized for field programmable gate array. To implement computationally efficient, low power, high-speed FIR filter a two-dimensional fully pipelined structure is used. The FIR filter is dynamically reconfigured to realize low pass and high pass filter by changing the filter coefficients. The FIR filter is most fundamental components in digital signal processing for high-speed application. The aim of this research work is to design multiplier-less FIR filter for the requirements of low power and high speed various embedded applications. 

A Modified Architecture of Multiplier and Accumulator Using Spurious Power Suppression Technique

2015 ◽  
Vol 3 (2) ◽  
pp. 258-263
Author(s):  
R. Mohanapriya ◽  
K. Rajesh
Keyword(s):  
High Speed ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Finite Impulse Response Filters ◽  
Look Ahead ◽  
Suppression Technique ◽  
Three Stages ◽  
Impulse Response Filters ◽  
Low Power Multiplier ◽  
Dsp Applications

High speed and low power Multiplier and Accumulator (MAC) unit is at most requirement of today’s VLSI systems and digital signal processing (DSP) applications like FFT, Finite Impulse response filters, convolution etc. In this modified architecture, Radix-4 Modified Booth Encoding (MBE) is used to produce the partial products. In this multiplication and accumulation has been combined using a hybrid type of Carry Save Adder (CSA). So the performance will be improved. A Carry Look ahead Adder is inserted in the CSA tree to reduce the number of bits in the final adder. In booth multiplication, when two numbers are multiplied some portion of the data may be zero. By neglecting those data, power has been reduced. For this purpose Spurious Power Suppression Technique (SPST) is used to remove useless portion of the data in addition process. In this modified architecture, the overall process is three stages to produce the result. The modified MAC operation is coded with Verilog and simulated using Xilinx 12.1.

scholarly journals Performance Analysis of High Speed and Area Efficient Finite Impulse Response Filters

2020 ◽  
Vol 12 (01) ◽  
pp. 8-12
Author(s):  
Md. Zakir Hussain ◽  
Kazi Nikhat Parvin
Keyword(s):  
Impulse Response ◽  
Software Defined Radio ◽  
High Speed ◽  
Finite Impulse Response ◽  
Finite Impulse Response Filters ◽  
Booth Multiplier ◽  
Look Ahead ◽  
Ripple Carry Adder ◽  
Windowing Technique ◽  
Impulse Response Filters

This study represents the designing and implementation of a bandpass finite impulse response (FIR) filter of order 31 using windowing techniques. The frequency parameters used are of a typical GSM receiver,19 which is one of the applications of software-defined radio (SDR). To minimize filter area, various multiplication techniques like a canonical signed digit, Vedic multiplier, booth multiplier, and modified booth multiplier are used. Adders like ripple carry adder, carry save adder, carry look ahead adder, and Kogge-Stone adder are used to add the product from the multiplier unit. A comparison between three different windows has been made. The FIR is designed in MATLAB using a windowing technique. Then it is synthesized on Xilinx 14.7, Virtex 6 XC6VLX760, whose results are included in this paper.

scholarly journals FFT using Power Efficient Vedic Multiplier

2019 ◽  
Vol 8 (10) ◽  
pp. 603-608
Keyword(s):  
Communication Systems ◽  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Power Efficient ◽  
Large Numbers ◽  
Vedic Multiplier ◽  
The Right ◽  
Dsp Systems ◽  
Minimal Area

Modern communication systems rely on Digital Signal Processing (DSP) more than ever before. Improving the speed of FFT computation using high speed multipliers will help to enhance the performance of DSP systems. In this paper a DIT FFT architecture using high performance Modified Vedic multipliers is proposed. Vedic Multipliers offer a more efficient way to perform multiplication on large numbers occupying less area and consuming low power and delay The adders used in the Vedic multipliers are Brent Kung based and multiplexer based adders. The right utilization of these adders at different word lengths helps to achieve an architecture with minimal area and power. Comparative analysis of modified 24×24 Vedic Multiplier with existing Vedic Multiplier shows the improvement in performance with respect to power and area. Proposed FFT design is compared with existing designs for dynamic power consumption and an improvement of 46.93% compared to Tsai’s FFT Design and 59.37% compared to Coelho’s FFT Design is achieved. The entire architecture is implemented on Virtex 7 FPGA and simulated using Xilinx Vivado 2017.4.

scholarly journals Design and Accomplishment of Fir Filters for High Accuracy Reconfigurable Applications

2019 ◽  
Vol 8 (11S) ◽  
pp. 96-99
Keyword(s):  
Finite Impulse Response ◽  
Low Complexity ◽  
High Accuracy ◽  
Fir Filter ◽  
Fir Filters ◽  
Finite Impulse Response Filters ◽  
Filter Arrangement ◽  
Impulse Response Filters ◽  
Filter Area ◽  
Selection Of

The top function of the job is to establish transpose style Finite Impulse Response filters. That is pipelined along with furthermore constantly aids a variety of regular Entertainments come close to that cause conserving of calculation. Change kind of filter arrangement does say goodbye to straight support the block taking care of process. The MCM is instead much safer in Transpose variety when the normal operand is a couple of with the celebration of routine coefficients that diminish the computational hold-up. The execution of MCM approach is much less complicated out of commission coefficient Transpose design FIR filter however centre in reconfigurable coefficients. In arranged coefficients change FIR filter, area equally as great as hold-up is decreased by making use of MCM strategy. The low-complexity kind utilizing the MCM system is made an application for dealt with coefficients change design FIR filters like multiplier-established design is benefited from for reconfigurable transpose kind FIR filter. Critiques of the end results obtained guidance that efficiency metrics of the recommended execution is considerably harmonies with academic presumptions. Moreover, the recommended FPGA energy lies to include substantially so much less discipline-delay complexity on the other hand with the controlling DA-established implementations of FIR filter. For the actually the very same filter measurement similar to the similar block measurement, the advertised constitution needs thirteen% a lot less ADP as well as also 12.8% a lot less EPS than that of the present direct-from obstructs FIR structure. Based on these findings, we provide a scheme for the selection of direct-type and also transpose-kind company based on the filter dimensions and also block-length for obtaining subject-extend as well as furthermore power superior block FIR frameworks.

scholarly journals Survey: Performance Analysis of FIR Filter Design Using Modified Truncation Multiplier with SQRT based Carry Select Adder

2018 ◽  
Vol 7 (2.32) ◽  
pp. 243
Author(s):  
U Penchalaiah ◽  
Siva Kumar VG
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
High Performance ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Large Area ◽  
Processing Application ◽  
Carry Select Adder ◽  
Fir Filter Design

A recent years of technology development in Signal processing application a FIR (Finite impulse response) filter design will have a highly compactable with high performance and low power in all digital signal processing application, such as audio processing, signal processing, software define radio and so on. Now a days in our environment will have more signal noises, and fluctuation due to technology development, here the Filter design is mainly configuring the priority to reduce the signal noises and fluctuation in all type of gadgets. In this project, the design contains Transpose form of high performance and high speed filter design using finite impulse response (FIR) filter with technique of pipelined inherently and supported multiple constant multiplication (MCM) in significant with saving power computation. In digital signal processing, the multiplier is a highly required thing, the example of parallel multiplier provide a high-speed and highly reliable method for multiplication, but this parallel multiplier will take large area and also power consumption. In the FIR filter design, multiplier and adders is the maximum priority will take to give the performance, but this MCM multiplier and Adders tree architecture will take large area and maximum power consumption in signal processing. So our Proposed approach of this work, will have replace the MCM multiplier to Truncated Multiplier and using the technique of Truncated based both Signed and Unsigned Operation with SQRT based Carry Select Adder (CSLA), and also replace the normal adders in FIR Filter to SQRT based Carry Select Adder (CSLA). In the proposed system of FIR Filter design results to be analysis with signed and unsigned Truncation using modified technique of HSCG-SCS based SQRT-CSLA and hence proved its more efficient than existing design, such as FIR filter for Truncation multiplier with SQRT-CSLA based Adders, FIR filter for Truncation multiplier with BEC based Adders, FIR filter for Truncation multiplier with RCA, and FIR filter for Truncation multiplier with Common Boolean logic based RCA, and finally implemented this design on VHDL with help of Xilinx FPGA-S6LX9 and shown the performance of proposed design in terms of delay, area, and power.

scholarly journals VLSI Architecture of High Performance Multiplier for High Speed Applications

2020 ◽  
Vol 9 (3) ◽  
pp. 442-445
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Vlsi Architecture ◽  
Digital Signal ◽  
Full Adder ◽  
Vital Role ◽  
Path Delay

In the application of digital signal process multipliers play a vital role. With advances in technology, several researchers have tried and try to design multipliers which supply high speed, low power consumption, regularity of layout and thus less space or maybe combination of them in one multiplier factor. Thus, Compact VLSI design for four bit multiplier factor is planned during this paper that is appropriate for low power and high speed applications. Multiplier factor with high performance is achieved through the novel style of hybrid single bit full adder and Dadda algorithmic rule. The important path delay and power consumption of the planned multiplier factor square measure reduced by 65.9% and 24.5% severally when put next with existing multipliers. The planned multiplier factor is synthesized exploitation CADENCE five.1.0 EDA tool and simulated exploitation spectre virtuoso.

scholarly journals HIGH PERFORMANCE ADAPTIVE FINITE IMPULSE RESPONSE FILTER USING NEW DISTRIBUTED ARITHMETIC ALGORITHM

2017 ◽  
Vol 10 (13) ◽  
pp. 352
Author(s):  
Sandeep Kumar ◽  
Vigneswaran T
Keyword(s):  
Parallel Processing ◽  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
High Performance ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Distributed Arithmetic ◽  
Power Filter ◽  
Arithmetic Algorithm

Finite Impulse Response (FIR) filters is very important in signal Processing Applications. This research is to analyze the performance of FIR filter with the Xilinx Software. The Distributed Arithmetic (DA) algorithm is extensively used in FIR Filter to improve its speed and reducing the area of the filter. The design of low power filter will be achieved by pipelining and parallel processing concept on distributed Arithmetic. The aim is to design filter which has less delay time and supports the pipelining/parallel processing feature, helps in high speed with less power dissipation and area. The paper discusses FPGA implementation of FIR filter and due to parallel data processing its computation is fast and also provides an efficient architecture in terms of area and power consumption. New Distributed   Arithmetic is a high performance and for low power filter.

scholarly journals EFFICIENT FINITE IMPULSE RESPONSE FILTER ARCHITECTURE USING MULTIPLE CONSTANT MULTIPLICATION AND COMMON SUB-EXPRESSION ELIMINATION TECHNIQUES

2017 ◽  
Vol 10 (13) ◽  
pp. 344
Author(s):  
Bhargav Shukla ◽  
Augusta Sophy Beulet
Keyword(s):  
Impulse Response ◽  
High Speed ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Computationally Efficient ◽  
Constant Multiplication ◽  
Dsp Systems ◽  
Fir Filter Design

This paper introduces the computationally efficient, low power, high-speed partial reconfigurable finite impulse response (FIR) filter design usingmultiple constant multiplication technique (MCM). The complexity of many digital signal processing (DSP) systems is reduced by MCM operation. Forthe better performance of DSP systems, MCM operation is not sufficient. To get better results, some other operations are used with MCM. That’s why,this paper introduces a common sub-expression elimination operation of FIR filter design can be solved by decreasing the number of operators. Usingthese techniques shows the efficiency by reducing area when compared to previously used algorithms designed.

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