Element Edge Based Discretization for TCAD Device Simulation

2021 ◽  
Author(s):  
Juan Sanchez ◽  
Qiusong Chen
Keyword(s):  
Computer Aided Design ◽  
Field Effect Transistor ◽  
Semiconductor Device ◽  
Device Simulation ◽  
Polarization Effects ◽  
Effect Transistor ◽  
Edge Based ◽  
Volume Method ◽  
Aided Design ◽  
Novel Devices

<div><div><div><p>Technology computer-aided design (TCAD) semiconductor device simulators solve partial differential equations (PDE) using the finite volume method (FVM), or related methods. While this approach has been in use over several decades, its methods continue to be extended, and are still applicable for investigating novel devices. In this paper, we present an element edge based (EEB) FVM discretization approach suitable for capturing vector-field effects. Drawing from a 2D approach in the literature, we have extended this method to 3D. We implemented this method in a TCAD semiconductor device simulator, which uses a generalized PDE (GPDE) approach to simulate de- vices with the FVM. We describe how our EEB method is compatible with the GPDE approach, allowing the modeling of vector effects using scripting. This method is applied to solve polarization effects in a 3D ferro capacitor, and a 2D ferroelectric field-effect transistor. An example for field- dependent mobility in a 3D MOSFET is also presented.</p></div></div></div>

scholarly journals Element Edge Based Discretization for TCAD Device Simulation

2021 ◽  
Author(s):  
Juan Sanchez ◽  
Qiusong Chen
Keyword(s):  
Computer Aided Design ◽  
Field Effect Transistor ◽  
Semiconductor Device ◽  
Device Simulation ◽  
Polarization Effects ◽  
Effect Transistor ◽  
Edge Based ◽  
Volume Method ◽  
Aided Design ◽  
Novel Devices

<div><div><div><p>Technology computer-aided design (TCAD) semiconductor device simulators solve partial differential equations (PDE) using the finite volume method (FVM), or related methods. While this approach has been in use over several decades, its methods continue to be extended, and are still applicable for investigating novel devices. In this paper, we present an element edge based (EEB) FVM discretization approach suitable for capturing vector-field effects. Drawing from a 2D approach in the literature, we have extended this method to 3D. We implemented this method in a TCAD semiconductor device simulator, which uses a generalized PDE (GPDE) approach to simulate de- vices with the FVM. We describe how our EEB method is compatible with the GPDE approach, allowing the modeling of vector effects using scripting. This method is applied to solve polarization effects in a 3D ferro capacitor, and a 2D ferroelectric field-effect transistor. An example for field- dependent mobility in a 3D MOSFET is also presented.</p></div></div></div>

scholarly journals Element Edge Based Discretization for TCAD Device Simulation

2021 ◽  
Author(s):  
Juan Sanchez ◽  
Qiusong Chen
Keyword(s):  
Computer Aided Design ◽  
Field Effect Transistor ◽  
Semiconductor Device ◽  
Ferroelectric Materials ◽  
Polarization Effects ◽  
Effect Transistor ◽  
Edge Based ◽  
Volume Method ◽  
Aided Design ◽  
Novel Devices

<div>Technology computer-aided design (TCAD) semiconductor device simulators solve partial differential equations (PDE) using the finite volume method (FVM), or related methods. While this approach has been in use over several decades, its methods continue to be extended, and are still applicable for investigating novel devices. In this paper, we present an element edge based (EEB) FVM discretization approach suitable for capturing vector-field effects. Drawing from a 2D approach in the literature, we have extended this method to 3D. We implemented this method in a TCAD semiconductor device simulator, which uses a generalized PDE (GPDE) approach to simulate devices with the FVM. We describe how our EEB method is compatible with the GPDE approach, allowing the modeling of vector effects using scripting. As an example, this method is applied to solve polarization effects in ferroelectric materials, with examples of a 3D ferro capacitor and a 2D ferroelectric field-effect transistor.</div>

scholarly journals Element Edge Based Discretization for TCAD Device Simulation

2021 ◽  
Author(s):  
Juan Sanchez ◽  
Qiusong Chen
Keyword(s):  
Computer Aided Design ◽  
Field Effect Transistor ◽  
Semiconductor Device ◽  
Ferroelectric Materials ◽  
Polarization Effects ◽  
Effect Transistor ◽  
Edge Based ◽  
Volume Method ◽  
Aided Design ◽  
Novel Devices

<div>Technology computer-aided design (TCAD) semiconductor device simulators solve partial differential equations (PDE) using the finite volume method (FVM), or related methods. While this approach has been in use over several decades, its methods continue to be extended, and are still applicable for investigating novel devices. In this paper, we present an element edge based (EEB) FVM discretization approach suitable for capturing vector-field effects. Drawing from a 2D approach in the literature, we have extended this method to 3D. We implemented this method in a TCAD semiconductor device simulator, which uses a generalized PDE (GPDE) approach to simulate devices with the FVM. We describe how our EEB method is compatible with the GPDE approach, allowing the modeling of vector effects using scripting. As an example, this method is applied to solve polarization effects in ferroelectric materials, with examples of a 3D ferro capacitor and a 2D ferroelectric field-effect transistor.</div>

scholarly journals Device and Circuit Exploration of Multi-Nanosheet Transistor for Sub-3 nm Technology Node

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 180
Author(s):  
Yoongeun Seon ◽  
Jeesoo Chang ◽  
Changhyun Yoo ◽  
Jongwook Jeon
Keyword(s):  
Integrated Circuit ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Semiconductor Device ◽  
Short Channel ◽  
Parasitic Resistance ◽  
Effect Transistor ◽  
And Performance ◽  
Aided Design

A multi-nanosheet field-effect transistor (mNS-FET) device was developed to maximize gate controllability while making the channel in the form of a sheet. The mNS-FET has superior gate controllability for the stacked channels; consequently, it can significantly reduce the short-channel effect (SCE); however, punch-through inevitably occurs in the bottom channel portion that is not surrounded by gates, resulting in a large leakage current. Moreover, as the size of the semiconductor device decreases to several nanometers, the influence of the parasitic resistance and parasitic capacitance increases. Therefore, it is essential to apply design–technology co-optimization, which analyzes not only the characteristics from the perspective of the device but also the performance from the circuit perspective. In this study, we used Technology Computer Aided Design (TCAD) simulation to analyze the characteristics of the device and directly fabricated a model that describes the current–voltage and gate capacitance characteristics of the device by using Berkeley short-channel insulated-gate field-effect transistor–common multi-gate (BSIM–CMG) parameters. Through this model, we completed the Simulation Program with Integrated Circuit Emphasis (SPICE) simulation for circuit analysis and analyzed it from the viewpoint of devices and circuits. When comparing the characteristics according to the presence or absence of bottom oxide by conducting the above research method, it was confirmed that subthreshold slope (SS) and drain-induced barrier lowering (DIBL) are improved, and power and performance in circuit characteristics are increased.

scholarly journals Demonstration of Fin-Tunnel Field-Effect Transistor with Elevated Drain

Micromachines ◽  
2019 ◽  
Vol 10 (1) ◽  
pp. 30 ◽  
Author(s):  
Jang Hyun Kim ◽  
Hyun Woo Kim ◽  
Garam Kim ◽  
Sangwan Kim ◽  
Byung-Gook Park
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Electrical Performance ◽  
Control Group ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Tcad Simulation ◽  
High Level ◽  
Aided Design

In this paper, a novel tunnel field-effect transistor (TFET) has been demonstrated. The proposed TFET features a SiGe channel, a fin structure and an elevated drain to improve its electrical performance. As a result, it shows high-level ON-state current (ION) and low-level OFF-state current (IOFF); ambipolar current (IAMB). In detail, its ION is enhanced by 24 times more than that of Si control group and by 6 times more than of SiGe control group. The IAMB can be reduced by up to 900 times compared with the SiGe control group. In addition, technology computer-aided design (TCAD) simulation is performed to optimize electrical performance. Then, the benchmarking of ON/OFF current is also discussed with other research group’s results.

I-Shaped SiGe Fin Tunnel Field-Effect Transistor with High ION/IOFF Ratio

2020 ◽  
Vol 20 (7) ◽  
pp. 4298-4302
Author(s):  
Ryoongbin Lee ◽  
Junil Lee ◽  
Kitae Lee ◽  
Soyoun Kim ◽  
Sihyun Kim ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Channel Width ◽  
Condensation Process ◽  
Performance Improvements ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design ◽  
Effective Channel

In this paper, we propose an I-shaped SiGe fin tunnel field-effect transistor (TFET) and use technology computer aided design (TCAD) simulations to verify the validity. Compared to conventional Fin TFET on the same footprint, a 27% increase in the effective channel width can be obtained with the proposed TFET. The proposed Fin TFET was confirmed to have 300% boosted on-current (I on), 25% reduced subthreshold swing (SS), and 52% lower off-current (I off) than conventional Fin TFET through TCAD simulation results. These performance improvements are attributed to increased effective channel width and enhanced gate controllability of the I-shaped fin structure. Furthermore, the fabrication process of forming an I-shaped SiGe fin is also presented using the SiGe wet etch. By optimizing the Ge condensation process, an I-shaped SiGe fin with a Ge ratio greater than 50% can be obtained.

scholarly journals Optimization of Tunnel Field-Effect Transistor-Based ESD Protection Network

Crystals ◽  
2021 ◽  
Vol 11 (2) ◽  
pp. 128
Author(s):  
Zhihua Zhu ◽  
Zhaonian Yang ◽  
Xiaomei Fan ◽  
Yingtao Zhang ◽  
Juin Jei Liou ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Source Region ◽  
Potential Candidate ◽  
Protection Scheme ◽  
Esd Protection ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design

The tunnel field-effect transistor (TFET) is a potential candidate for replacing the reverse diode and providing a secondary path in a whole-chip electrostatic discharge (ESD) protection network. In this paper, the ESD characteristics of a traditional point TFET, a line TFET and a Ge-source TFET are investigated using technology computer-aided design (TCAD) simulations, and an improved TFET-based whole-chip ESD protection scheme is proposed. It is found that the Ge-source TFET has a lower trigger voltage and higher failure current compared to the traditional point and line TFETs. However, the Ge-source TFET-based secondary path in the whole-chip ESD protection network is more vulnerable compared to the primary path due to the low thermal instability. Simulation results show that choosing the proper germanium mole fraction in the source region can balance the discharge ability and thermal failure risk, consequently enhancing the whole-chip ESD robustness.

scholarly journals Tool Setup Improvement for Package Scratch Mitigation at End-of-Line Process

2020 ◽  
pp. 1-5
Author(s):  
A. Sumagpang Jr. ◽  
F. R. Gomez ◽  
R. Rodriguez
Keyword(s):  
Computer Aided Design ◽  
Semiconductor Device ◽  
Device Simulation ◽  
Actual Process ◽  
Semiconductor Technology ◽  
Computer Aided ◽  
Line Process ◽  
Process Replication ◽  
Aided Design ◽  
Technology Trends

With new and continuous semiconductor technology trends, challenges in assembly manufacturing are inevitable. This paper focused on the elimination of assembly defects particularly package chip-out and scratch at the singulation end-of-line (EOL) process of a semiconductor device.  Simulation using computer-aided design (CAD) tools, actual process replication, and validations were done, eventually verifying and replicating the desired defect signatures. Singulation tool setup of the package was improved and a standardized tool setup was established based on the simulation and actual validations, resulting to at least 90% improvement in assembly EOL process parts per million (ppm) reduction.

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