scholarly journals A single D.C. link Multi-level 42-sided polygonal Voltage Space Vector Generation with lower order harmonic suppression using Switched-Capacitive filter

Author(s):  
Gopakumar K ◽  
Rahul Dewani, ◽  
Umanand L ◽  
leopoldo Franquelo ◽  
Rajashekara Kaushik

<div>In this work, a multi-level 42-sided polygonal space vector structure (SVS) for suppression of lower order harmonics for Open-End Induction Motor(OEIM) drive applications is proposed. The proposed power circuit topology consists of two inverters feeding an Open-End Induction Motor from either side. The main inverter fed with a single DC link providing active power for motor operation is switched at low switching frequency. The secondary inverter fed with a capacitive supply is switched at high frequency to suppress lower order harmonics upto 39th order, up to the base speed of operation allowing maximum utilization of the DC link. The advantages of lower order harmonic suppression in motor phase voltage, for polygonal space vector structures are combined with multi-level inverter topology. This results in lower switching losses in low frequency switching main inverter and low voltage secondary inverter. Use of a single DC link facilitates fourquadrant operation of the inverter. The proposed scheme is validated for steady state and dynamic performance by experimental results.</div>

2021 ◽  
Author(s):  
Gopakumar K

<div>Abstract—In this work, a multi-level 42-sided polygonal space vector structure (SVS) for suppression of lower order harmonics for Open-End Induction Motor(OEIM) drive applications is proposed. The proposed power circuit topology consists of two inverters feeding an Open-End Induction Motor from either side. The main inverter fed with a single DC link providing active power for motor operation is switched at low switching frequency. The secondary</div><div>inverter fed with a capacitive supply is switched at high frequency to suppress lower order harmonics upto 39th order, up to the base speed of operation allowing maximum utilization of the DC link. The advantages of lower order harmonic suppression in motor phase voltage, for polygonal space vector structures are combined with multi-level inverter topology. This results in lower switching losses in low frequency switching main inverter and low voltage secondary inverter. Use of a single DC link facilitates four quadrant operation of the inverter. The proposed scheme is validated for steady state and dynamic performance by experimental results.</div>


2021 ◽  
Author(s):  
Gopakumar K

<div>Abstract—In this work, a multi-level 42-sided polygonal space vector structure (SVS) for suppression of lower order harmonics for Open-End Induction Motor(OEIM) drive applications is proposed. The proposed power circuit topology consists of two inverters feeding an Open-End Induction Motor from either side. The main inverter fed with a single DC link providing active power for motor operation is switched at low switching frequency. The secondary</div><div>inverter fed with a capacitive supply is switched at high frequency to suppress lower order harmonics upto 39th order, up to the base speed of operation allowing maximum utilization of the DC link. The advantages of lower order harmonic suppression in motor phase voltage, for polygonal space vector structures are combined with multi-level inverter topology. This results in lower switching losses in low frequency switching main inverter and low voltage secondary inverter. Use of a single DC link facilitates four quadrant operation of the inverter. The proposed scheme is validated for steady state and dynamic performance by experimental results.</div>


2021 ◽  
Author(s):  
Gopakumar K ◽  
Rahul Dewani, ◽  
Umanand L ◽  
leopoldo Franquelo ◽  
Rajashekara Kaushik

<div>In this work, a multi-level 42-sided polygonal space vector structure (SVS) for suppression of lower order harmonics for Open-End Induction Motor(OEIM) drive applications is proposed. The proposed power circuit topology consists of two inverters feeding an Open-End Induction Motor from either side. The main inverter fed with a single DC link providing active power for motor operation is switched at low switching frequency. The secondary inverter fed with a capacitive supply is switched at high frequency to suppress lower order harmonics upto 39th order, up to the base speed of operation allowing maximum utilization of the DC link. The advantages of lower order harmonic suppression in motor phase voltage, for polygonal space vector structures are combined with multi-level inverter topology. This results in lower switching losses in low frequency switching main inverter and low voltage secondary inverter. Use of a single DC link facilitates fourquadrant operation of the inverter. The proposed scheme is validated for steady state and dynamic performance by experimental results.</div>


Author(s):  
Amirah J. Mohammed ◽  
◽  
Raaed F. Hassan

The work presented in this paper aims to compare the effectiveness of different control strategies to improve the performance of the three-phase Induction Motor (IM). The Conventional Direct Torque Control (CDTC) was employed as the first strategy for driving the IM. This control strategy causes high ripples in the IM's torque and speed due to the hysteresis comparators and a variable switching frequency due to the look-up table. A modified DTC strategy based on Space Vector Modulation (DTC-SVM) was chosen as a second strategy to enhance the performance of the IM using the two-level inverter. This method, which leads to the reduction of the torque and speed ripples and achieves constant switching frequency. As the multi-level inverter becomes most popular than the two-level inverter, the third strategy is devoted to adopting the three-level flying capacitor inverter (TLFCMLI) -based DTC-SVM. The third strategy uses the method of mapping the multi-level space vector based on basic two-level SVM. Matlab/Simulink software package is utilized to implement the suggested controllers. Simulation results show that the DTC-SVM based on TLFCMLI significantly enhances the IM's performance compared with the other two strategies from the voltage and current profiles, torque, and speed points of view.


This paper deals with sensorless vector controlled induction motor in which torque pulsations are reduced with improved input of induction motor. In proposed technique two multi winding transformers are used for generation of 18 sinusoidal signals given to rectifier unit and the rectifier output given as input to 9 level multi level inverter. In this proposed technique gating signals to the inverter switches will be provided through space vector pulse width modulation which considers speed as reference. This configuration was simulated in MATLAB/Simulink.and the simulation results are presented here with improvement in reduction of THD.


2021 ◽  
Author(s):  
Jingya Dai

The rapid growth of wind energy market has propelled the research and development of high-power wind turbines in the megawatt range. At this power level, current source converter (CSC) topologies possess favorable features such as simple structure, grid friendly waveforms, controllable power factor, and reliable grid short-circuit protection. This dissertation proposes the use of current source converters for permanent magnet synchronous generator based megawatt wind energy conversion systems (WECS). Related research in terms of converter topology, modulation scheme, control strategy and grid integration are carried out to adapt the proposed configuration for megawatt wind applications. Various current source converter topologies are compared for wind applications. Detailed feasibility study and performance evaluation are conducted based on theoretical analysis and simulation results. Among all, the back-to-back pulse-width modulated (PWM) current source converter is identified as the most promising converter configuration for megawatt WECS due to its high performance, control flexibility and compliance with grid connection codes. A novel multi-sampling space vector modulation (MS-SVM) scheme with superior harmonic performance and controllability is proposed to operate the PWM CSC. The device switching frequency under MS-SVM is investigated and methods to eliminate additional switching are presented. The proposed scheme is compared with the conventional modulation schemes. It is demonstrated that the MS-SVM scheme provides superior performance at low switching frequency. It not only offers high control flexibility but also substantially reduces the low-order harmonics existing in the conventional schemes. System modeling and controller design for the current source converter based WECS are then presented. Dynamic, steady-state and small-signal models are developed for analysis and controller design. An optimum de-link current control scheme is developed to achieve the best dynamic performance and maximize the system overall efficiency. Control strategies such as decoupled active and reactive power control and power feed-forward control are also proposed to further improve the system dynamic performance. Grid integration issues, especially the low-voltage ride-through capability of the current source converter based WECS, are addressed. Challenges for the grid-connected current source converter are identified based on grid code requirements. A unified de-link current control scheme is proposed to assist the system to ride through grid low-voltage faults while maintaining the control capability of active and reactive power during and after the fault. The unified de-link controller can be well embedded in the system control structure. Smooth transitions between normal and fault operations are achieved. Simulation and experimental verifications for various objectives are provided throughout the dissertation. The results validate the proposed solutions for the main challenges of using current source converter in a megawatt WECS.


2021 ◽  
Author(s):  
Jiacheng Wang

High-power multimodular matrix converters (MMMCs) comprising multiple threephase to single-phase matrix converter modules have emerged as a viable topology candidate for medium-voltage adjustable speed drives. As a combination of direct power conversion and cascaded multilevel structure, the MMMCs inherit features such as elimination of dc capacitors, four quadrant operation capability, employment of lowvoltage devices only, and superior output waveform quality under a limited device switching frequency. Due to their particular topological structure, modulation scheme design for the MMMCs is not straightforward and complicated. The presented work is mainly focused on development of suitable modulation schemes for the MMMCs. Several viable schemes as well as their corresponding switching patterns are proposed and verified by both simulation and experimental results. In order for the MMMCs to produce sinusoidal waveforms at both input and output ac terminals, a direct transfer matrix based modulation scheme is presented. It is revealed that a suitable modulation strategy for the MMMCs should aim at fabricating the total input current on the primary side of the isolation transformer. For topologies with more than two modules in cascade on each output phase, switching period displacement is necessary among modules to generate multilevel output waveforms. An indirect space vector based modulation scheme for the MMMCs is developed. With a few presumptions satisfied and viewed from a certain perspective, the MMMCs can still be modeled indirectly and be divided into fictitious rectifier and inverter stages. Therefore, space vector modulation methods can be independently applied to both stages for duty ratio calculation, before the results are converted and combined for determining per-phase output pulses. A new output switching pattern providing improved harmonic performance is also proposed. A novel modulation scheme based on diode rectifier emulation and phase-shifted sinusoidal pulse-width modulation is proposed. The method sacrifices input power factor adjustment, but enables the use of an indirect module construction leading to significantly reduced device count and complexity. Strategy for reducing additional switchings caused by input voltage ripples is also implemented and explained. In addition to simulation verifications, all the proposed schemes are further tested experimentally on a low-voltage prototype built in the lab. Details about the prototype implementation are introduced.


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