scholarly journals Implementation and Design of 32 Bit Floating-Point ALU on a Hybrid FPGA-ARM Platform

2019 ◽  
Vol 1 (1) ◽  
pp. 26-32
Author(s):  
Bahadır ÖZKILBAÇ
Keyword(s):  
Neural Network ◽  
Image Processing ◽  
Integrated Circuit ◽  
Floating Point ◽  
Low Power Consumption ◽  
Arm Processor ◽  
Large Numbers ◽  
Floating Point Number ◽  
Hybrid Fpga ◽  
Logic Unit

FPGAs have capabilities such as low power consumption, multiple I/O pins, and parallel processing. Because of these capabilities, FPGAs are commonly used in numerous areas that require mathematical computing such as signal processing, artificial neural network design, image processing and filter applications. From the simplest to the most complex, all mathematical applications are based on multiplication, division, subtraction, addition. When calculating, it is often necessary to deal with numbers that are fractional, large or negative. In this study, the Arithmetic Logic Unit (ALU), which uses multiplication, division, addition, subtraction in the form of IEEE754 32-bit floating-point number used to represent fractional and large numbers is designed using FPGA part of the Xilinx Zynq-7000 integrated circuit. The programming language used is VHDL. Then, the ALU designed by the ARM processor part of the same integrated circuit was sent by the commands and controlled.

Neural network training based on FPGA with floating point number format and it’s performance

2010 ◽  
Vol 20 (2) ◽  
pp. 195-202 ◽  
Author(s):  
Mehmet Ali Çavuşlu ◽  
Cihan Karakuzu ◽  
Suhap Şahin ◽  
Mehmet Yakut
Keyword(s):  
Neural Network ◽  
Floating Point ◽  
Neural Network Training ◽  
Network Training ◽  
Point Number ◽  
Floating Point Number

scholarly journals A Test Data Compression Scheme Based on Irrational Numbers Stored Coding

2014 ◽  
Vol 2014 ◽  
pp. 1-7 ◽  
Author(s):  
Hai-feng Wu ◽  
Yu-sheng Cheng ◽  
Wen-fa Zhan ◽  
Yi-fei Cheng ◽  
Qiong Wu ◽  
...  
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Integrated Circuit ◽  
Irrational Number ◽  
Floating Point ◽  
Test Data Compression ◽  
Compression Scheme ◽  
Test Question ◽  
Irrational Numbers ◽  
Floating Point Number

Test question has already become an important factor to restrict the development of integrated circuit industry. A new test data compression scheme, namely irrational numbers stored (INS), is presented. To achieve the goal of compress test data efficiently, test data is converted into floating-point numbers, stored in the form of irrational numbers. The algorithm of converting floating-point number to irrational number precisely is given. Experimental results for some ISCAS 89 benchmarks show that the compression effect of proposed scheme is better than the coding methods such as FDR, AARLC, INDC, FAVLC, and VRL.

scholarly journals Design of High Speed FFT using Urdhva-Tiryagbhyam Algorithm and Karatsuba Algorithm

2020 ◽  
Vol 9 (4) ◽  
pp. 1904-1908
Keyword(s):  
Image Processing ◽  
Signal Processing ◽  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Execution Time ◽  
Communication Systems ◽  
High Speed ◽  
Floating Point ◽  
Calculation Algorithms ◽  
Floating Point Number

In gift scenario each method has to be compelled to be quick, adept and simple. Fast Fourier transform (FFT) may be a competent algorithmic program to calculate the N purpose Discrete Fourier transform (DFT).It has huge applications in communication systems, signal processing and image processing and instrumentation. However the accomplishment of FFT needs immense range of complicated multiplications, therefore to create this method quick and simple. It’s necessary for a number to be quick and power adept. To influence this problem the mixture of Urdhva Tiryagbhyam associate degreed Karatsuba algorithmic program offers is an adept technique of multiplication [1]. Vedic arithmetic is that the aboriginal system of arithmetic that includes a distinctive technique of calculation supported sixteen Sutras. Using these techniques within the calculation algorithms of the coprocessor can reduce the complexness, execution time, area, power etc. The distinctiveness during this project is Fast Fourier Transform (FFT) style methodology exploitation mixture of Urdhva Tiryagbhyam and Karatsuba algorithmic program based mostly floating point number. By combining these two approaches projected style methodology is time-area-power adept [1] [2]. The code writing is completed in verilog and also the FPGA synthesis on virtex 5 is completed using Xilinx ISE 14.5.

In-Line Defect to Bitmap Signature Correlation: A Shortcut to Physical FA Results

2000 ◽  
Author(s):  
Julie Segal ◽  
Arman Sagatelian ◽  
Bob Hodgkins ◽  
Tom Ho ◽  
Ben Chu ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Failure Mechanisms ◽  
Memory Devices ◽  
Line Defect ◽  
Yield Improvement ◽  
Electrical Test ◽  
Large Numbers ◽  
Improvement Process ◽  
Existing Data

Abstract Physical failure analysis (FA) of integrated circuit devices that fail electrical test is an important part of the yield improvement process. This article describes how the analysis of existing data from arrayed devices can be used to replace physical FA of some electrical test failures, and increase the value of physical FA results. The discussion is limited to pre-repair results. The key is to use classified bitmaps and determine which signature classification correlates to which type of in-line defect. Using this technique, physical failure mechanisms can be determined for large numbers of failures on a scale that would be unfeasible with de-processing and physical FA. If the bitmaps are classified, two-way correlation can be performed: in-line defect to bitmap failure, as well as bitmap signature to in-line defect. Results also demonstrate the value of analyzing memory devices failures, even those that can be repaired, to gain understanding of defect mechanisms.

scholarly journals Neural network aided approximation and parameter inference of non-Markovian models of gene expression

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Qingchao Jiang ◽  
Xiaoming Fu ◽  
Shifu Yan ◽  
Runlai Li ◽  
Wenli Du ◽  
...  
Keyword(s):  
Neural Network ◽  
Stochastic Dynamics ◽  
Stochastic Simulations ◽  
Parameter Inference ◽  
Biochemical Processes ◽  
Markovian Models ◽  
The Neural Network ◽  
Large Numbers ◽  
Small Set ◽  
Noisy Measurements

AbstractNon-Markovian models of stochastic biochemical kinetics often incorporate explicit time delays to effectively model large numbers of intermediate biochemical processes. Analysis and simulation of these models, as well as the inference of their parameters from data, are fraught with difficulties because the dynamics depends on the system’s history. Here we use an artificial neural network to approximate the time-dependent distributions of non-Markovian models by the solutions of much simpler time-inhomogeneous Markovian models; the approximation does not increase the dimensionality of the model and simultaneously leads to inference of the kinetic parameters. The training of the neural network uses a relatively small set of noisy measurements generated by experimental data or stochastic simulations of the non-Markovian model. We show using a variety of models, where the delays stem from transcriptional processes and feedback control, that the Markovian models learnt by the neural network accurately reflect the stochastic dynamics across parameter space.

scholarly journals Convolutional Neural Network for the Semantic Segmentation of Remote Sensing Images

2021 ◽  
Vol 26 (1) ◽  
pp. 200-215
Author(s):  
Muhammad Alam ◽  
Jian-Feng Wang ◽  
Cong Guangpei ◽  
LV Yunrong ◽  
Yuanfang Chen
Keyword(s):  
Neural Network ◽  
Remote Sensing ◽  
Neural Networks ◽  
Image Processing ◽  
Deep Learning ◽  
Semantic Segmentation ◽  
Natural Scene ◽  
Remote Sensing Images ◽  
Advantages And Disadvantages ◽  
Target Segmentation

AbstractIn recent years, the success of deep learning in natural scene image processing boosted its application in the analysis of remote sensing images. In this paper, we applied Convolutional Neural Networks (CNN) on the semantic segmentation of remote sensing images. We improve the Encoder- Decoder CNN structure SegNet with index pooling and U-net to make them suitable for multi-targets semantic segmentation of remote sensing images. The results show that these two models have their own advantages and disadvantages on the segmentation of different objects. In addition, we propose an integrated algorithm that integrates these two models. Experimental results show that the presented integrated algorithm can exploite the advantages of both the models for multi-target segmentation and achieve a better segmentation compared to these two models.

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