In-Line Defect to Bitmap Signature Correlation: A Shortcut to Physical FA Results

2000 ◽  
Author(s):  
Julie Segal ◽  
Arman Sagatelian ◽  
Bob Hodgkins ◽  
Tom Ho ◽  
Ben Chu ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Failure Mechanisms ◽  
Memory Devices ◽  
Line Defect ◽  
Yield Improvement ◽  
Electrical Test ◽  
Large Numbers ◽  
Improvement Process ◽  
Existing Data

Abstract Physical failure analysis (FA) of integrated circuit devices that fail electrical test is an important part of the yield improvement process. This article describes how the analysis of existing data from arrayed devices can be used to replace physical FA of some electrical test failures, and increase the value of physical FA results. The discussion is limited to pre-repair results. The key is to use classified bitmaps and determine which signature classification correlates to which type of in-line defect. Using this technique, physical failure mechanisms can be determined for large numbers of failures on a scale that would be unfeasible with de-processing and physical FA. If the bitmaps are classified, two-way correlation can be performed: in-line defect to bitmap failure, as well as bitmap signature to in-line defect. Results also demonstrate the value of analyzing memory devices failures, even those that can be repaired, to gain understanding of defect mechanisms.

Scanning Optical Microscopy Application in Micron® Memory Devices

2005 ◽  
Author(s):  
Wong Yaw Yuan ◽  
T.L. Edmund Poh ◽  
David Lam
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Fault Isolation ◽  
Memory Devices ◽  
Back Side ◽  
Induced Voltage ◽  
Scanning Optical Microscopy ◽  
Side Emission ◽  
Complex Circuits

Abstract The migration to smaller geometries has translated to an increase in the number of transistors possible in each integrated circuit. Failure analysis of such complex circuits presents a major challenge to the semiconductor industry and is a driving force behind the considerable interest in nondestructive, cost-efficient, “shortcut” fault isolation techniques. In this paper, we present the application of thermal-induced voltage alteration (TIVA) for failure analysis of 0.11µm technology memory devices and demonstrate the key aspects of this technique. The back side TIVA results are compared with analysis performed using back side emission microscopy (EMMI), and the limitations of EMMI are highlighted. The advantages and limitations of the TIVA technique are also discussed.

In-Line Defects Overlaying with Functional Failures and Characterization for Fast Defect Learning and Fast Yield Improvement

2014 ◽  
Author(s):  
Zhigang Song ◽  
Oliver D. Patterson ◽  
Qian Xu
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
Semiconductor Device ◽  
Development Stage ◽  
Line Defect ◽  
Defect Inspection ◽  
Yield Improvement ◽  
Root Cause ◽  
Manufacturing Yield ◽  
The Impact

Abstract Process defects, either random or systematic, are often the top killers of any semiconductor device. Process defect learning and reduction are the main focuses in both technology development stage and product manufacturing yield ramp stage. In order to achieve fast defect learning, in-line defect inspection is implemented in critical layers during wafer manufacturing. In-line defect inspection is able to detect defects. However, in-line defect inspection alone cannot predict the impact of defects on device functional yield. Failure analysis is an effective method of finding the defects which really cause device functional failures. However, often, the defects found by failure analysis are very different from the original defects, making it difficult to understand the root cause. This paper will describe a methodology how to combine in-line defect inspection and failure analysis together to found the top killer defects and accelerate their root cause identification for fast defect learning and yield improvement.

Novel Failure Analysis Sample Preparation Techniques for PoP Packaging

2012 ◽  
Author(s):  
Ng Sea Chooi ◽  
Chor Theam Hock ◽  
Ma Choo Thye ◽  
Khoo Poh Tshin ◽  
Dan Bockelman
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Failure Mechanisms ◽  
Preparation Process ◽  
Space Saving ◽  
Optical Probing ◽  
Preparation Techniques

Abstract Trends in the packaging of semiconductors are towards miniaturization and high functionality. The package-on-package(PoP) with increasing demands is beneficial in cost and space saving. The main failure mechanisms associated with PoP technology, including open joints and warpage, have created a lot of challenges for Assembly and Failure Analysis (FA). This paper outlines the sample preparation process steps to overcome the challenges to enable successful failure analysis and optical probing.

Failure Analysis of CDM-ESD Damage in a GaAs RFIC

2000 ◽  
Author(s):  
Amy Poe ◽  
Steve Brockett ◽  
Tony Rubalcava
Keyword(s):  
Radio Frequency ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Production Test ◽  
Analysis Techniques ◽  
Device Model ◽  
Charged Device ◽  
Subsequent Failure

Abstract The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.

Failure Analysis of Single Shared Column Fail in DRAM Using Nano-Probing Technique

2008 ◽  
Author(s):  
Suk Min Kim ◽  
Jung Ho Lee ◽  
Jong Hak Lee ◽  
Hyung Ki Kim ◽  
Myung Sick Chang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Electrical Characteristics ◽  
The Future ◽  
Electrical Analysis

Abstract We report an analysis of a single shared column fail on DRAM technology using a nano-probing technique in this work. The electrical characteristics of the failed transistors show that the column fails were caused by two different failure mechanisms: abnormal contact and implant profiles. We believe that electrical analysis using nano-probing will be a powerful tool for non-visible failure analysis in the future because it is impossible to clearly reveal these two different failure mechanisms solely using physical failure methods.

Rapid Failure Analysis of Low-Yielding Electrical Test Structures Using E-beam Physical and Voltage Contrast Inspection

2013 ◽  
Author(s):  
Oliver D. Patterson ◽  
Deborah A. Ryan ◽  
Xiaohu Tang ◽  
Shuen Cheng Lei
Keyword(s):  
Failure Analysis ◽  
Defect Detection ◽  
High Volume ◽  
The Other ◽  
Defect Inspection ◽  
Electrical Test ◽  
Detection Mode ◽  
Rapid Generation ◽  
Voltage Contrast ◽  
Additional Support

Abstract In-line E-beam inspection may be used for rapid generation of failure analysis (FA) results for low yielding test structures. This approach provides a number of advantages: 1) It is much earlier than traditional FA, 2) de-processing isn’t required, and 3) a high volume of sites can be processed with the additional support of an in-line FIB. Both physical defect detection and voltage contrast inspection modes are useful for this application. Voltage contrast mode is necessary for isolation of buried defects and is the preferred approach for opens, because it is faster. Physical defect detection mode is generally necessary to locate shorts. The considerations in applying these inspection modes for rapid failure analysis are discussed in the context of two examples: one that lends itself to physical defect inspection and the other, more appropriately addressed with voltage contrast inspection.

Advanced IR-OBIRCH Analysis Technique for High Isb Failure Analysis

2010 ◽  
Author(s):  
Kuo Hsiung Chen ◽  
Wen Sheng Wu ◽  
Yu Hsiang Shu ◽  
Jian Chan Lin
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Fault Localization ◽  
Resistance Change ◽  
The Real ◽  
Analysis Techniques ◽  
Analysis Technique ◽  
Leakage Failure ◽  
Failure Site

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.

Application of Fast Laser Deprocessing Techniques in Physical Failure Analysis on SRAM Memory of Advance Technology

2014 ◽  
Author(s):  
H.H. Yap ◽  
P.K. Tan ◽  
G.R. Low ◽  
M.K. Dawood ◽  
H. Feng ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Cost Effective ◽  
Tetraethyl Orthosilicate ◽  
Ic Design ◽  
Advance Technology ◽  
Defect Identification ◽  
Technology Scaling ◽  
And Function ◽  
Metal Layers

Abstract With technology scaling of semiconductor devices and further growth of the integrated circuit (IC) design and function complexity, it is necessary to increase the number of transistors in IC’s chip, layer stacks, and process steps. The last few metal layers of Back End Of Line (BEOL) are usually very thick metal lines (>4μm thickness) and protected with hard Silicon Dioxide (SiO2) material that is formed from (TetraEthyl OrthoSilicate) TEOS as Inter-Metal Dielectric (IMD). In order to perform physical failure analysis (PFA) on the logic or memory, the top thick metal layers must be removed. It is time-consuming to deprocess those thick metal and IMD layers using conventional PFA workflows. In this paper, the Fast Laser Deprocessing Technique (FLDT) is proposed to remove the BEOL thick and stubborn metal layers for memory PFA. The proposed FLDT is a cost-effective and quick way to deprocess a sample for defect identification in PFA.

Combine Micro-Probing and OBIRCH to Catch Non-Recognizable Fault in RF and Mixed-Mode Integrated Circuits

2007 ◽  
Author(s):  
Cha-Ming Shen ◽  
Yen-Long Chang ◽  
Lian-Fon Wen ◽  
Tan-Chen Chuang ◽  
Shi-Chen Lin ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Radio Frequency ◽  
Failure Analysis ◽  
Case Studies ◽  
Mixed Mode ◽  
Failure Mechanisms ◽  
Deep Submicron ◽  
Digital Logic ◽  
Successful Approach ◽  
Cmos Processes

Abstract Highly-integrated radio frequency and mixed-mode devices that are manufactured in deep-submicron or more advanced CMOS processes are becoming more complex to analyze. The increased complexity presents us with many eccentric failure mechanisms that are uniquely different from traditional failure mechanisms found during failure analysis on digital logic applications. This paper presents a novel methodology to overcome the difficulties and discusses two case studies which demonstrate the application of the methodology. Through the case studies, the methodology was proven to be a successful approach. It is also proved how this methodology would work for such non-recognizable failures.

Application of AFP in Resolving Systematic Issue in Wafer Fabrication

2013 ◽  
Author(s):  
Hui Peng Ng ◽  
Ghim Boon Ang ◽  
Chang Qing Chen ◽  
Alfred Quah ◽  
Angela Teo ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Failure Mechanisms ◽  
Critical Role ◽  
Electrical Characterization ◽  
Process Technology ◽  
Atomic Force ◽  
Defect Localization ◽  
Non Volatile Memory ◽  
Visual Failure

Abstract With the evolution of advanced process technology, failure analysis is becoming much more challenging and difficult particularly with an increase in more erratic defect types arising from non-visual failure mechanisms. Conventional FA techniques work well in failure analysis on defectively related issue. However, for soft defect localization such as S/D leakage or short due to design related, it may not be simple to identify it. AFP and its applications have been successfully engaged to overcome such shortcoming, In this paper, two case studies on systematic issues due to soft failures were discussed to illustrate the AFP critical role in current failure analysis field on these areas. In other words, these two case studies will demonstrate how Atomic Force Probing combined with Scanning Capacitance Microscopy were used to characterize failing transistors in non-volatile memory, identify possible failure mechanisms and enable device/ process engineers to make adjustment on process based on the electrical characterization result. [1]

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