Optimization of Linearity in CMOS Low Noise Amplifier

2012 ◽  
pp. 1-14
Author(s):  
Thierry Taris ◽  
Aya Mabrouki
Keyword(s):  
Power Consumption ◽  
Drain Current ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
The Third ◽  
Operating Region ◽  
Promising Solution ◽  
Noise Amplifier

In this chapter the authors evaluate a new and promising solution to the problem of power consumption based on “optimum gate biasing.” This technique consists in tracking the MOS operating region wherein the third derivation of drain current is zero. The method leads to a significant IIP3 improvement; however, the sensitivity to process drifts requires the use of a specific bias circuit to track the optimum biasing condition.

scholarly journals 2.4 GHZ HETERODYNE RECEIVER FOR HEALTHCARE APPLICATION

2016 ◽  
Vol 8 (2) ◽  
pp. 22 ◽  
Author(s):  
Wei Cai ◽  
Frank Shi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Tuning Range ◽  
Low Noise ◽  
Heterodyne Receiver ◽  
The Third ◽  
Noise Amplifier ◽  
Lc Tank ◽  
Down Conversion

<p class="lead">The objective of this research was to design a basic 2.4 GHz heterodyne receiver for healthcare on a 130um CMOS process. The ultimate goal for the wireless industry is to minimize the trade-offs between performance and cost, and between performance and low power consumption design. In the first part, a low noise amplifier (LNA), which is commonly used as the first stage of a receiver, is introduced and simulated. LNA performance greatly affects the overall receiver performance. The LNA was designed at the 2.4 GHz ISM band, using the cascode with an inductive degeneration topology. The second part of this thesis presents a low power 2.4 GHz down conversion Gilbert Cell mixer. In the third part, a high-performance LC-tank CMOS VCO was designed at 2.4 GHz. The design uses using PMOS cross-coupled topology with the varactor for wider tuning range topology. In the first part, a low noise amplifier (LNA) design reaches the NF of 2 dB, has a power consumption of 2.2 mW, and has a gain of 20dB. The second part of this proposal presents a low power 2.4 GHz down conversion Gilbert Cell mixer. The obtained result shows a conversion gain of 14.6 dB and power consumption of 8.2 mW at a 1.3V supply voltage. In the third part, a high-performance LC-tank CMOS VCO was designed at 2.4 GHz. The final simulation of the phase noise is-128 dBc/Hz, and the tuning range is 2.3 GHz-2.5 GHz while the total power consumption is 3.25 mW.<strong> </strong>The performance of the receiver meets the specification requirements of the desired standard.</p>

A 0.1–1.4 GHz inductorless low-noise amplifier with 13 dBm IIP3 and 24 dBm IIP2 in 180 nm CMOS

2018 ◽  
Vol 32 (02) ◽  
pp. 1850009 ◽  
Author(s):  
Benqing Guo ◽  
Jun Chen ◽  
Hongpeng Chen ◽  
Xuebing Wang
Keyword(s):  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Voltage Gain ◽  
Third Order ◽  
Weak Inversion ◽  
Linearization Technique ◽  
The Third ◽  
Noise Amplifier ◽  
Second Order Nonlinearity

An inductorless noise-canceling CMOS low-noise amplifier (LNA) with wideband linearization technique is proposed. The complementary configuration by stacked NMOS/PMOS is employed to compensate second-order nonlinearity of the circuit. The third-order distortion of the auxiliary stage is also mitigated by that of the weak inversion transistors in the main path. The bias and scaling size combined by digital control words are further tuned to obtain enhanced linearity over the desired band. Implemented in a 0.18 [Formula: see text]m CMOS process, simulated results show that the proposed LNA provides a voltage gain of 16.1 dB and a NF of 2.8–3.4 dB from 0.1 GHz to 1.4 GHz. The IIP3 and IIP2 of 13–18.9 and 24–40 dBm are obtained, respectively. The circuit core consumes 19 mW from a 1.8 V supply.

Design of High Performance Low-Noise Amplifier Circuit Based on Complementary Metal Oxide Semiconductor Technology

2021 ◽  
Vol 16 (4) ◽  
pp. 559-564
Author(s):  
Chao Huang ◽  
Wan-Jun Yin
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Input Device ◽  
Output Stage ◽  
Noise Amplifier ◽  
5 Ghz

This paper designs a body-biased (BB) differential cascode low-noise amplifier (LNA) with current bias (CR) and capacitor cross-coupling (CCC) technology that meets the bandwidth requirements of 5 GHz wireless applications. In the design, the CCC technology in the differential cascode topology is used to effectively suppress the common mode noise, thereby improving the noise figure. The series resonant network eliminates parasitic capacitance at the input and output ends, thereby improving the power transmission efficiency. The CR technology formed by the intermediate capacitor shares the DC current input to the output device, thereby increasing the gain. This paper uses BB technology in the design to lower the threshold of the cascode device and improve the transconductance, which further improves the gain and reduces the power consumption. The CCC technology used in the paper improves linearity by eliminating the non-linear components present in the input device, which will not interfere with the transconductance of the output stage. This article has obtained excellent performance parameters including gain, noise figure (NF) and linearity without affecting the power consumption, integration and cost of the proposed design.

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