Lightweight VLSI Architectures for Image Encryption Applications

2022 ◽  
Vol 16 (1) ◽  
pp. 0-0

Lightweight cryptography offers significant security service in constrained environments such as wireless sensor networks and Internet of Things. The focus of this article is to construct lightweight SPN block cipher architectures with substitution box based on finite fields. The paper also details the FPGA implementation of the lightweight symmetric block cipher algorithm of SPN type with combinational S-box. Restructuring of traditional look-up-table Substitution Box (S-Box) sub-structure with a combinational logic S-box is attempted. Elementary architectures namely the basic round architecture and reduced datawidth architecture incorporating look-up-table and combinational S-Box substructure are compared in terms of area and throughput. Proposed restructure mechanism occupies less FPGA resources with no comprise in the latency and also demonstrates performance efficiency and low power consumption in Xilinx FPGAs. Robustness of the proposed method against various statistical attacks has been analyzed through comparison with other existing encryption mechanisms.

2012 ◽  
Vol 73 (3) ◽  
pp. 731-740 ◽  
Author(s):  
Hanen Thabet ◽  
Stéphane Meillère ◽  
Mohamed Masmoudi ◽  
Jean-Luc Seguin ◽  
Hervé Barthelemy ◽  
...  

Author(s):  
N. Mohananthini ◽  
M. Y. Mohamed Parvees ◽  
J. Abdul Samath

Nowadays, lightweight cryptography attracts academicians, scientists and researchers to concentrate on its requisite with the increasing usage of low resource devices. In this paper, a new lightweight image encryption scheme is proposed using the Lorenz 3D super chaotic map. This encryption scheme is an addition–rotation–XOR block cipher designed for its supremacy, efficacy and speed execution. In this addition–rotation–XOR cipher, the equation for Lorenz 3D chaotic map is iteratively solved to generate double valued signals in a speedy manner using the Runge–Kutta and Euler methods. The addition, rotation and diffusion sequences are generated from the double valued signals, and the source pixels of the 8-bit plain test images are manipulated with the addition, rotation and diffusion of the bytes. Finally, the cipher images are constructed from the manipulated pixels and evaluated with various statistical as well as randomness tests. The results from various tests prove that the proposed chaotic addition–rotation–XOR block image cipher is efficient in terms of randomness and speed.


Sensors ◽  
2019 ◽  
Vol 19 (4) ◽  
pp. 913 ◽  
Author(s):  
Sa’ed Abed ◽  
Reem Jaffal ◽  
Bassam Mohd ◽  
Mohammad Alshayeji

Security of sensitive data exchanged between devices is essential. Low-resource devices (LRDs), designed for constrained environments, are increasingly becoming ubiquitous. Lightweight block ciphers provide confidentiality for LRDs by balancing the required security with minimal resource overhead. SIMON is a lightweight block cipher targeted for hardware implementations. The objective of this research is to implement, optimize, and model SIMON cipher design for LRDs, with an emphasis on energy and power, which are critical metrics for LRDs. Various implementations use field-programmable gate array (FPGA) technology. Two types of design implementations are examined: scalar and pipelined. Results show that scalar implementations require 39% less resources and 45% less power consumption. The pipelined implementations demonstrate 12 times the throughput and consume 31% less energy. Moreover, the most energy-efficient and optimum design is a two-round pipelined implementation, which consumes 31% of the best scalar’s implementation energy. The scalar design that consumes the least energy is a four-round implementation. The scalar design that uses the least area and power is the one-round implementation. Balancing energy and area, the two-round pipelined implementation is optimal for a continuous stream of data. One-round and two-round scalar implementations are recommended for intermittent data applications.


IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 165536-165550 ◽  
Author(s):  
Cuong Trinh ◽  
Bao Huynh ◽  
Jan Lansky ◽  
Stanislava Mildeova ◽  
Masoumeh Safkhani ◽  
...  

Author(s):  
Haiying Huang ◽  
Yayu Hew

This paper presents the implementation and characterization of a low power wireless vibration sensor that can be powered by a flash light. The wireless system consists of two components, namely the wireless sensor node and the wireless interrogation unit. The wireless sensor node includes a wireless strain gauge that consumes around 6 mW, a signal modulation circuit, and a light energy harvesting unit. To achieve ultra-low power consumption, the signal modulation circuit was implemented using a voltage-controlled oscillator (VCO) to convert the strain gauge output to an intermediate frequency (IF) signal, which is then used to alter the impedance of the sensor antenna and thus achieves amplitude modulation of the backscattered antenna signal. A generic solar panel with energy harvesting circuit is used to power the strain sensor node continuously. The wireless interrogation unit transmits the interrogation signal and receives the amplitude modulated antenna backscattering, which can be down-converted to recover the IF signal. In order to measure the strains dynamically, a Phase Lock Loop (PLL) circuit was implemented at the interrogator to track the frequency of the IF signal and provide a signal that is directly proportional to the measured strain. The system features ultra-low power consumption, complete wireless sensing, solar powering, and portability. The application of this low power wireless strain system for vibration measurement is demonstrated and characterized.


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