An FPGA Based Color Bar Signal Generator for PAL Standard

2013 ◽  
Vol 433-435 ◽  
pp. 1419-1422
Author(s):  
Yang Liu ◽  
Yong Tie ◽  
Ming Li Xiao ◽  
Shun Na

Color bar signal generator is one of the most important measurements for PAL TV applications. However, its use in resource constrained applications such as color TV video adjustment is limited because of the high architecture complexity involved. Due to the broad range of applications presently offered by FPGA (filed programmable gate array), their use has become increasingly widespread in different areas and sectors. In this paper, we present the design and implementation of a color bar signal generator based on FPGA and MC1377 with a high performance and low system complexity. The FPGA technology proved to be a proper platform to meet these two contrasting requirements. The signal structure, generation principle, and FPGA implementation of composite PAL synchronize signal and RGB color signal are described. The interface circuits, hardware and software of the system are introduced. The software is simulated using MAXplusII platform. Simulation results indicate the effectiveness and stability of the signal generator.

Sensors ◽  
2021 ◽  
Vol 21 (8) ◽  
pp. 2715
Author(s):  
Ruth Yadira Vidana Morales ◽  
Susana Ortega Cisneros ◽  
Jose Rodrigo Camacho Perez ◽  
Federico Sandoval Ibarra ◽  
Ricardo Casas Carrillo

This work illustrates the analysis of Film Bulk Acoustic Resonators (FBAR) using 3D Finite Element (FEM) simulations with the software OnScale in order to predict and improve resonator performance and quality before manufacturing. This kind of analysis minimizes manufacturing cycles by reducing design time with 3D simulations running on High-Performance Computing (HPC) cloud services. It also enables the identification of manufacturing effects on device performance. The simulation results are compared and validated with a manufactured FBAR device, previously reported, to further highlight the usefulness and advantages of the 3D simulations-based design process. In the 3D simulation results, some analysis challenges, like boundary condition definitions, mesh tuning, loss source tracing, and device quality estimations, were studied. Hence, it is possible to highlight that modern FEM solvers, like OnScale enable unprecedented FBAR analysis and design optimization.


Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 288
Author(s):  
Adam Wolniakowski ◽  
Charalampos Valsamos ◽  
Kanstantsin Miatliuk ◽  
Vassilis Moulianitis ◽  
Nikos Aspragathos

The determination of the optimal position of a robotic task within a manipulator’s workspace is crucial for the manipulator to achieve high performance regarding selected aspects of its operation. In this paper, a method for determining the optimal task placement for a serial manipulator is presented, so that the required joint torques are minimized. The task considered comprises the exercise of a given force in a given direction along a 3D path followed by the end effector. Given that many such tasks are usually conducted by human workers and as such the utilized trajectories are quite complex to model, a Human Robot Interaction (HRI) approach was chosen to define the task, where the robot is taught the task trajectory by a human operator. Furthermore, the presented method considers the singular free paths of the manipulator’s end-effector motion in the configuration space. Simulation results are utilized to set up a physical execution of the task in the optimal derived position within a UR-3 manipulator’s workspace. For reference the task is also placed at an arbitrary “bad” location in order to validate the simulation results. Experimental results verify that the positioning of the task at the optimal location derived by the presented method allows for the task execution with minimum joint torques as opposed to the arbitrary position.


2012 ◽  
Vol 542-543 ◽  
pp. 769-774
Author(s):  
Qun Ling Yu ◽  
Na Bai ◽  
Yan Zhou ◽  
Rui Xing Li ◽  
Jun Ning Chen ◽  
...  

A new technique for reducing the offset of latch-type sense amplifier has been proposed and effect of enable signal voltage upon latch-type sense amplifier offset in SRAM has been investigated in this paper. Circuit simulation results on both StrongARM and Double-tail topologies show that the standard deviation of offset can be reduced by 31.23% (StrongARM SA) and 25.2% (Double-tail SA) , respectively, when the voltage of enable signal reaches 0.6V in TSMC 65nm CMOS technology. For a column of bit-cell (1024 bit-cell), the total speed is improved by 14.98% (StrongARAM SA) and 22.26% (Double-tail SA) at the optimal operation point separately, and the total energy dissipation is reduced by 30.45% and 29.47% with this scheme.


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