Design and Simulation of an Improved Five Redundancy GNC System Architecture

2014 ◽  
Vol 543-547 ◽  
pp. 1423-1427
Author(s):  
Yue Lin ◽  
Ya Nan Gao ◽  
Song Tao Fan ◽  
Chun Xu

Aerospace plane, the next generation manned spacecraft has the characteristics of high reliability and high security. Therefore, a five modular redundancy byzantine fault tolerant architecture is propose for the guidance, navigation and control (GNC) system. This architecture can give the system characteristic of double fault resilience, and is also suitable for solving Byzantine general problem. A semi-physical simulation is done, which is based on 1553B data bus and VxWorks operating system. The simulation result has verified the fault tolerant architecture and feasibility of the system implementation.

2020 ◽  
Vol 35 (1) ◽  
pp. 51-67
Author(s):  
A.S.A. Al-Masri ◽  

RN-659 cars are essential to ensure high reliability and stability of the international computer communication system. This case looks at the RNA C659 Series ray tracing model and debris failure mechanism. According to the pilot, a computer anti-aircraft system consisting of 4 aircraft was created. In addition, a computer and computer development program were created for the computer's command and screen components. Computer Security Management System does not complete invalid cards, computer votes, and sub-monitoring and control instructions.


2019 ◽  
pp. 258-264
Author(s):  
Sergey F. Tyurin

The so-called Fault-Tolerant Systems (FTS) use the structural, temporal, functional, or information redundancy for the achievement of the high reliability. For example, Radiation Hardened by Design (RHBD) Systems are Fault-Tolerant Systems. A Passive FTS, due to a very large structural redundancy (Modular Redundancy), produces faults masking. The Triple Modular Redundancy (TMR) Method has more than 300% redundancy. The Quad Redundancy (QR) Method boasts more than 400% redundancy. The CMOS transistors QR (transistor-level redundancy) is the most effective QR. In this case, no voting element is needed. However, this significantly increases the time delay. In addition, it is necessary to ensure compliance with the Mead-Conway restrictions. QR, in contrast to TMR, raises the problem of checking the redundant structure. The author proposes a QR Checking Method based on a selection of substrates of the CMOS transistors. The power lines of the transistor substrates are separated, which ensures the disconnection of part of the reserve. A simulation confirms the feasibility of the proposed method.


2014 ◽  
Vol 573 ◽  
pp. 209-214
Author(s):  
B. Sargunam ◽  
R. Dhanasekaran

The use of finite field multipliers in the critical applications like elliptic curve cryptography needs Concurrent Error Detection (CED) and correction at architectural level to provide high reliability. This paper discusses fault tolerant technique for polynomial representation based finite field multipliers. The detection and correction are done on-line. We use a combination of Double Modular Redundancy (DMR) and Concurrent Error Detection (CED) techniques. The fault tolerant finite field multiplier is coded in VHDL and simulated using Modelsim. Further, the proposed multiplier with fault tolerant capability is synthesized and results are analyzed with respect to area occupied, input and output pin counts and delay. Our technique, when compared with existing techniques, gives better performance. We show that our concurrent error detecting multiplier over GF(2m) requires less than 200% extra hardware, whereas with the traditional fault tolerant techniques, such as Triple Modular Redundancy (TMR), overhead is more than 200%.


Author(s):  
C. CHELLAPPAN ◽  
G. VIJAYALAKSHMI

With the increasing demand for high reliability in mission critical systems such as space shuttle, digital flight and real time control to mention a few, reliability analysis of fault tolerant systems continues to be the focus of most researchers. The reliability analysis of triple modular redundancy (TMR) and hybrid redundancy (TMR with spares) systems is in general carried out with the assumption of failure rate being precise. However, in practice failure rate is imprecise due to the uncertainties of system operation. In this paper, the dependability analysis of hybrid redundancy systems (HRS) comprising of N-modular redundancy (NMR) and standby redundancy is presented assuming failure rates and repair rates as fuzzy numbers. Each module of the NMR is assumed to have access to a number of cold spares and a repair facility. A Markov model for the HRS is developed. As the Markov model parameters may not be precisely known due to various reasons, vertex method and α-cut method is applied. These methods allow uncertainty-based parameters that are represented as fuzzy numbers. The dependability measures such as availability and reliability are obtained. A comparative study of the fuzzy results and the conventional results using probability concepts is presented.


2017 ◽  
Vol 8 (1) ◽  
pp. 3-7 ◽  
Author(s):  
R. Şinca ◽  
CS. Szász

The paper presents a fault-tolerant digital system design and development strategy for high reliability hardware architectures implementation. Starting from the general consideration that digital hardware systems play a key role in a large scale of control systems implementation, a triple modular redundancy (TMR) solution it is proposed for development. For this reason, the well-known 1 bit majority voter configuration has been extended and generalized to the full control bus of a digital control system. Computer simulations show that the proposed hardware solution fulfills in all the theoretical expectations and it can be used for experimental tests and implementation. The presented design solution and conclusions are well suited to generalization for a wide range of fault-tolerant digital systems development ranging from reliable and safety servo control applications up to high reliability parallel and distributed computing hardware architectures.


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