The Effect of Etchant Concentration and Temperature on Surface Finish of Silicon Wafer Thinning

2015 ◽  
Vol 1115 ◽  
pp. 29-32
Author(s):  
M.A. Safaruddin ◽  
S.F.M. Shahar ◽  
I.H. Jaafar

Fabrication of silicon (Si) wafer microfilters via focus ion beam (FIB) sputtering (milling/drilling) is planned. However, due to limitations of FIB sputtering, the wafer has to be initially thinned to a certain thickness to ensure that micron-scale through holes can be successfully manufactured. This paper reports on thinning of a silicon wafer via wet chemical etching using 15, 20, and 25% w/w potassium hydroxide (KOH) at 3 different etchant temperatures (80oC, 90oC, and 100oC). The target is to achieve 100 μm with the lowest time taken and wafer surface roughness after etching. From the experiments conducted, it was determined that KOH solution at 15% w/w concentration at 100oC produced the best result with an etch rate of 5.43 μm/min, surface roughness (Ra) of 0.12μm and thickness of 123.00μm.

2009 ◽  
Vol 69-70 ◽  
pp. 253-257
Author(s):  
Ping Zhao ◽  
Jia Jie Chen ◽  
Fan Yang ◽  
K.F. Tang ◽  
Ju Long Yuan ◽  
...  

Semi-fixed abrasive is a novel abrasive. It has a ‘trap’ effect on the hard large grains that can prevent defect effectively on the surface of the workpiece which is caused by large grains. In this paper, some relevant experiments towards silicon wafers are carried out under the different processing parameters on the semi-fixed abrasive plates, and 180# SiC is used as large grains. The processed workpieces’ surface roughness Rv are measured. The experimental results show that the surface quality of wafer will be worse because of higher load and faster rotating velocity. And it can make a conclusion that the higher proportion of bond of the plate, the weaker of the ‘trap’ effect it has. Furthermore the wet environment is better than dry for the wafer surface in machining. The practice shows that the ‘trap’ effect is failure when the workpiece is machined by abrasive plate which is 4.5wt% proportion of bond in dry lapping.


2008 ◽  
Vol 389-390 ◽  
pp. 493-497 ◽  
Author(s):  
Sung Chul Hwang ◽  
Jong Koo Won ◽  
Jung Taik Lee ◽  
Eun Sang Lee

As the level of Si-wafer surface directly affects device line-width capability, process latitude, yield, and throughput in fabrication of microchips, it needs to have ultra precision surface and flatness. Polishing is one of the important processing having influence on the surface roughness in manufacturing of Si-wafers. The surface roughness in wafer polishing is mainly affected by the many process parameters. For decreasing the surface roughness, the control of polishing parameters is very important. In this paper, the optimum condition selection of ultra precision wafer polishing and the effect of polishing parameters on the surface roughness were evaluated by the statistical analysis of the process parameters.


Author(s):  
Naoya Watanabe ◽  
Takumi Miyazaki ◽  
Kazuhiro Yoshikawa ◽  
Masahiro Aoyagi

1992 ◽  
Vol 279 ◽  
Author(s):  
Wei Chen ◽  
P. Chen ◽  
A. Madhukar ◽  
R. Viswanathan ◽  
J. So

ABSTRACTWe report the realization of free standing 3D structures as tall as ∼ 7μm with nano-scale thickness in Si using the technique of Ga focused ion beam implantation and sputtering followed by wet chemical etching. Some of the previously investigated subjects such as anisotropie etching behavior of crystalline Si and etch stop effect of Ga+implanted Si etched in certain anisotropie chemical etchants have been further explored with the emphasis on exploiting them in realizing free standing structures. The design and fabrication considerations in achieving such free standing structures are discussed and some typical structures fabricated by this technique are shown.


2003 ◽  
Vol 76 (7) ◽  
pp. 1109-1112 ◽  
Author(s):  
A. Crunteanu ◽  
G. Jänchen ◽  
P. Hoffmann ◽  
M. Pollnau ◽  
C. Buchal ◽  
...  

2020 ◽  
Vol 59 (40) ◽  
pp. 17680-17688
Author(s):  
Lena Mohr ◽  
Tobias Dannenberg ◽  
Anamaria Moldovan ◽  
Martin Zimmer ◽  
Claas Müller

2010 ◽  
Vol 2010 (1) ◽  
pp. 000505-000512
Author(s):  
Mohammad K. Chowdhury ◽  
Li Sun ◽  
Shawn J. Cunningham ◽  
Ajay P. Malshe

The objective of the research is to understand the effect of chemical treatment's etching times on via wall roughness; and the direct current (DC) and reverse pulse plating (RPP) of vias fabricated using micro mechanical punching process on liquid crystal polymer (LCP) substrate. One major drawback of micro mechanical punching process is the formation of LCP and copper burrs. Sequential wet chemical etching and oxygen plasma cleaning techniques were developed as an effective tool for the removal of these burrs. The wet chemical process required a sequential oxidation, etching, and acid neutralization treatment for the effective removal of LCP and copper burrs. These treatments have an effect on the surface roughness of the through via wall. Under this research time dependent experimental matrices were designed to observe the effect of the wet chemical etching on the via wall surface roughness. Sequential oxidation, etching, and acid neutralization treatments were done, where only one treatment time was varied for 1, 5, and 10 minutes keeping the other treatment times constant at 5 minutes. After examining three different experimental matrices for via wall roughness using a scanning electron microscope (SEM), it was observed that the longer treatment time using chemical etchant will make the surface rougher. In addition, it was also observed that the oxidation treatment time of greater than 5 minutes produced the same roughness irrespective of treatment time variation. The neutralization treatment time does not have any effect on the roughness of the LCP via wall. Two different approaches named - DC and reverse pulse plating (RPP) were used to plate the vias. It was found that the RPP does not result in good via filling, because it produced high current concentration at the edges and consequently over plating at the edge compared to the inside of the via. In stark contrast, DC plating delivers completely plated vias after 4.5 hours, which is a 7 μm/hr plating rate.


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