Implementation of Intelligent Video Analysis System and it’s Algorithm Optimization Based on DSP

2011 ◽  
Vol 403-408 ◽  
pp. 217-222
Author(s):  
Hui Wang ◽  
Cheng Wu Liang ◽  
Ying Li
Keyword(s):  
Image Processing ◽  
Video Analysis ◽  
Digital Signal Processor ◽  
Digital Signal ◽  
Optimization Techniques ◽  
Algorithm Optimization ◽  
Automatic Tracking ◽  
Analog Channels ◽  
Analysis System ◽  
Algorithm Level

This paper aims to implement an distributed intelligent video analysis system based on TI multimedia Digital Signal Processor (DSP) TMS320DM642, at the same time, the algorithm optimization is also described. The intelligent video analysis system we proposed provides users with fast and precise video analysis services. The video image is transmitted to the image processing board by analog channels and IP cameras, then the DSP processing the video flow. In this system, target detection, segmentation, feature extraction, alarm and automatic tracking can be implemented. In this system, several optimization techniques are also used in algorithms, including the algorithm level optimization (ALO), the program level optimization (PLO) and the instruction level optimization (ILO). Experimental results show the exellent result in reducing the CPU load.

scholarly journals Optimizing Convolution Neural Network on the TI C6678 multicore DSP

2018 ◽  
Vol 246 ◽  
pp. 03044 ◽  
Author(s):  
Guozhao Zeng ◽  
Xiao Hu ◽  
Yueyue Chen
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Image Processing ◽  
Deep Learning ◽  
Digital Signal Processor ◽  
High Performance ◽  
Digital Signal ◽  
Automatic Translation ◽  
Convolution Operation ◽  
Multicore Dsp

Convolutional Neural Networks (CNNs) have become the most advanced algorithms for deep learning. They are widely used in image processing, object detection and automatic translation. As the demand for CNNs continues to increase, the platforms on which they are deployed continue to expand. As an excellent low-power, high-performance, embedded solution, Digital Signal Processor (DSP) is used frequently in many key areas. This paper attempts to deploy the CNN to Texas Instruments (TI)’s TMS320C6678 multi-core DSP and optimize the main operations (convolution) to accommodate the DSP structure. The efficiency of the improved convolution operation has increased by tens of times.

scholarly journals Design of Low Power and High Speed 4X4 Multiplier using Modified Column Bypassing Scheme for DSP Applications

2019 ◽  
Vol 8 (2S3) ◽  
pp. 643-647
Keyword(s):  
Low Power ◽  
Digital Signal Processor ◽  
High Speed ◽  
Vlsi Design ◽  
Digital Signal ◽  
Cmos Technology ◽  
Optimization Techniques ◽  
Operating Voltage ◽  
Booth Encoder ◽  
Dsp Applications

In this paper a low power and high speed 4X4 multiplier is designed using CMOS Technology. The important factors in VLSI Design are power, area, speed and design time. Now-a-days, power and speed has become a crucial factor in Digital Signal Processor (DSP) Applications. However, different optimization techniques are available in the digital electronic world. The proposed approach a Low power and high speed Multiplier Design based on Modified Column bypassing technique mainly used to reduce the switching power activity. While this technique offers great dynamic power savings, due to their interconnection. In this work, a low power and high speed multiplier with Hybridization scheme is presented. This scheme is combination of booth encoder algorithm and column bypass technique is called modified column bypassing scheme. The simulations are performed in 0.18µm CMOS Technology in Cadence Virtuoso tools with operating voltage ±1.8v

scholarly journals Implementation and Optimization of Image Processing on the Map of SABRE i.MX_6

2021 ◽  
pp. 402-417
Author(s):  
Waheed Muhammad SANYA ◽  
Gaurav BAJPAI ◽  
Haji Ali HAJI
Keyword(s):  
Image Processing ◽  
Image Denoising ◽  
Median Filter ◽  
Random Noise ◽  
Optimization Techniques ◽  
Image Process ◽  
Algorithm Optimization ◽  
Visual Appearance ◽  
Algorithmic Optimization ◽  
Different Response

Vision relieves humans to understand the environmental deviations over a period. These deviations are seen by capturing the images. The digital image plays a dynamic role in everyday life. One of the processes of optimizing the details of an image whilst removing the random noise is image denoising. It is a well-explored research topic in the field of image processing. In the past, the progress made in image denoising has advanced from the improved modeling of digital images. Hence, the major challenges of the image process denoising algorithm is to advance the visual appearance whilst preserving the other details of the real image. Significant research today focuses on wavelet-based denoising methods. This research paper presents a new approach to understand the Sobel imaging process algorithm on the Linux platform and develop an effective algorithm by using different optimization techniques on SABRE i.MX_6. Our work concentrated more on the image process algorithm optimization. By using the OpenCV environment, this paper is intended to simulate a Salt and Pepper noisy phenomenon and remove the noisy pixels by using Median Filter Algorithm. The Sobel convolution method included and used in the design of a Sobel Filter and then process the image following the median filter, to achieve an effective edge detection result. Finally, this paper optimizes the algorithm on SABRE i.MX_6 Linux environment. By using algorithmic optimization (lower complexity algorithm in the mathematical sense, using appropriate data structures), optimization for RISC (loop unrolling) processors, including optimization for efficient use of hardware resources (access to data, cache management and multi-thread), this paper analyzed the different response parameters of the system with varied inputs, different compiler options (O1, O2, or O3), and different doping degrees. The proposed denoising algorithm shows the meaningful addition of the visual quality of the images and the algorithmic optimization assessment.

The Research and Design of Image Processing System Based on FPGA and DSP

2014 ◽  
Vol 886 ◽  
pp. 556-559 ◽  
Author(s):  
Su Hua Chen ◽  
Zhi Meng Shu ◽  
Xu Fang
Keyword(s):  
Image Processing ◽  
Embedded System ◽  
Digital Signal Processor ◽  
High Speed ◽  
High Performance ◽  
Processing System ◽  
Image Data ◽  
Digital Signal ◽  
System A ◽  
High Efficient

In order to improve high performance and low power of image processing embedded system, A high-efficient image processing embedded system which is based on the field programmable gate array and high-speed digital signal processor in this paper. In the whole system, A novel data transmission structure with a dual-port RAM which is divided into two halves, is applied to buff the high-speed real-time image data by Ping-pong technique. Because all work in the system is divided between the FPGA and DSP in the form of the pipelined, it is 25% higher than the processing system based on the single DSP in performance.

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