Crystal Plasticity Analysis of Thermal Deformation and Dislocation Accumulation in ULSI Cells

2006 ◽  
Vol 324-325 ◽  
pp. 1035-1038 ◽  
Author(s):  
Michihiro Sato ◽  
Tetsuya Ohashi ◽  
Takuya Maruizumi ◽  
Isao Kitagawa
Keyword(s):  
Crystal Plasticity ◽  
Thermal Deformation ◽  
Room Temperature ◽  
Friction Stress ◽  
High Temperature Region ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Half Loop ◽  
The Difference ◽  
Lattice Friction

Thermal stress, plastic slip deformation and accumulation of dislocations in shallow trench isolation (STI) type ULSI devices when the temperature drops from 1000 し to room temperature are analyzed by a crystal plasticity analysis cord. The results show that dislocation accumulation takes place at the temperature range over 800 し, and the difference of 6 MPa in the lattice friction stress at 1000 し!causes increase of dislocation density more than 1.6 times. Dislocations generate and accumulate at the shoulder part of the device area and bottom corners of the trench. Dislocations are categorized into two groups. In one group, dislocation lines are mostly straight and parallel to the trench direction, and in the other group, dislocations make half loop type structure. Possibilities for the suppression of dislocation accumulation through control of lattice friction stress at high temperature region are discussed.

Crystal Plasticity Analysis of Dislocation Accumulation in ULSI Cells with Consideration of Temperature Dependence of the Lattice Friction Stress for Silicon

2007 ◽  
Vol 340-341 ◽  
pp. 199-204 ◽  
Author(s):  
Michihiro Sato ◽  
Tetsuya Ohashi ◽  
Takuya Maruizumi ◽  
Isao Kitagawa
Keyword(s):  
Crystal Plasticity ◽  
Large Scale ◽  
Friction Stress ◽  
Device Fabrication ◽  
Temperature Range ◽  
Trench Isolation ◽  
Large Scale Integration ◽  
The Difference ◽  
Scale Integration ◽  
Lattice Friction

Representative length scale of ULSI (Ultra Large Scale Integration) cells is going to be at a nano-meter order, and the atomic level defects, such as uneven oxide films or dislocation accumulation are becoming more and more important. Among these defects, dislocation accumulation is known to be caused by thermo-plastic deformation in silicon during the processes of device fabrication. In this study, we analyse such thermal stress, plastic slip deformation and accumulation of dislocations in STI (Shallow Trench Isolation) type ULSI devices when the temperature drops from the initial at 1000 °C to room temperature. For the analysis, we use a crystal plasticity analysis code CLP, assuming that lattice friction stress for the movement of dislocations is proportional to the hardness of silicon, which is known to have strong dependency on temperature. The results show that dislocations are generated between the temperature range from 880 to 800 °C, and its maximum density is highly dependent on the lattice friction stress in the temperature range above 800 °C. For example, the difference of 16 MPa in the lattice friction stress at 1000 °C caused increase in dislocation density more than ten times. It is concluded that control of lattice friction stress at high temperatures is one of the most promising way for the suppression of dislocation accumulation.

Simulation of Dislocation Accumulation in ULSI Cells of Reduced Gate Length

2010 ◽  
Vol 654-656 ◽  
pp. 1682-1685 ◽  
Author(s):  
Michihiro Sato ◽  
Tetsuya Ohashi ◽  
Keisuke Aikawa ◽  
Takuya Maruizumi ◽  
Isao Kitagawa
Keyword(s):  
Periodic Structure ◽  
Crystal Plasticity ◽  
Semiconductor Device ◽  
Temperature Drop ◽  
Gate Length ◽  
Initial Value ◽  
Device Structure ◽  
Shallow Trench Isolation ◽  
Trench Isolation

We numerically evaluate the accumulation of dislocations in periodic structure of the shallow trench isolation (STI) type ULSI cells which has generally been adopted as the latest semiconductor device structure. STI type ULSI cells with gate length less than 62 nm and various trench depths are employed and subjected to a temperature drop from the initial value of 1000 °C. Dislocation accumulation is evaluated by a technique of crystal plasticity analysis. Relations between the geometry of the STI type ULSI cells and dislocation accumulation are discussed.

Micro-Raman Spectroscopy Evaluation of the Local Mechanical Stress in Shallow Trench Isolation CMOS Structures: Correlation with Defect Generation and Diode Leakage

1998 ◽  
Author(s):  
I. De Wolf ◽  
G. Groeseneken ◽  
H.E. Maes ◽  
M. Bolt ◽  
K. Barla ◽  
...  
Keyword(s):  
Raman Spectroscopy ◽  
Mechanical Stress ◽  
Defect Formation ◽  
Active Area ◽  
Wet Oxidation ◽  
Leakage Currents ◽  
Shallow Trench Isolation ◽  
Micro Raman Spectroscopy ◽  
Silicon Devices ◽  
Trench Isolation

Abstract It is shown, using micro-Raman spectroscopy, that Shallow Trench Isolation introduces high stresses in the active area of silicon devices when wet oxidation steps are used. These stresses result in defect formation in the active area, leading to high diode leakage currents. The stress levels are highest near the outer edges of line structures and at square structures. They also increase with decreasing active area dimensions.

Advances in Chemical-Mechanical Planarization

MRS Bulletin ◽  
2002 ◽  
Vol 27 (10) ◽  
pp. 743-751 ◽  
Author(s):  
Rajiv K. Singh ◽  
Rajeev Bajaj
Keyword(s):  
Surface Topography ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Chemical Mechanical Planarization ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Fundamental Understanding ◽  
Copper Polishing ◽  
Future Growth

AbstractThe primary aim of this issue of MRS Bulletin is to present an overview of the materials issues in chemical–mechanical planarization (CMP), also known as chemical–mechanial polishing, a process that is used in the semiconductor industry to isolate and connect individual transistors on a chip. The CMP process has been the fastest-growing semiconductor operation in the last decade, and its future growth is being fueled by the introduction of copper-based interconnects in advanced microprocessors and other devices. Articles in this issue range from providing a fundamental understanding of the CMP process to the latest advancements in the field. Topics covered in these articles include an overview of CMP, fundamental principles of slurry design, understanding wafer–pad–slurry interactions, process integration issues, the formulation of abrasive-free slurries for copper polishing, understanding surface topography issues in shallow trench isolation, and emerging applications.

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