Simulation of Dislocation Accumulation in ULSI Cells of Reduced Gate Length

2010 ◽  
Vol 654-656 ◽  
pp. 1682-1685 ◽  
Author(s):  
Michihiro Sato ◽  
Tetsuya Ohashi ◽  
Keisuke Aikawa ◽  
Takuya Maruizumi ◽  
Isao Kitagawa
Keyword(s):  
Periodic Structure ◽  
Crystal Plasticity ◽  
Semiconductor Device ◽  
Temperature Drop ◽  
Gate Length ◽  
Initial Value ◽  
Device Structure ◽  
Shallow Trench Isolation ◽  
Trench Isolation

We numerically evaluate the accumulation of dislocations in periodic structure of the shallow trench isolation (STI) type ULSI cells which has generally been adopted as the latest semiconductor device structure. STI type ULSI cells with gate length less than 62 nm and various trench depths are employed and subjected to a temperature drop from the initial value of 1000 °C. Dislocation accumulation is evaluated by a technique of crystal plasticity analysis. Relations between the geometry of the STI type ULSI cells and dislocation accumulation are discussed.

Gate length dependence of the shallow trench isolation leakage current in an irradiated deep submicron NMOSFET

2011 ◽  
Vol 32 (6) ◽  
pp. 064004 ◽  
Author(s):  
Zhangli Liu ◽  
Zhiyuan Hu ◽  
Zhengxuan Zhang ◽  
Hua Shao ◽  
Ming Chen ◽  
...  
Keyword(s):  
Leakage Current ◽  
Deep Submicron ◽  
Gate Length ◽  
Shallow Trench Isolation ◽  
Length Dependence ◽  
Trench Isolation

Crystal Plasticity Analysis of Thermal Deformation and Dislocation Accumulation in ULSI Cells

2006 ◽  
Vol 324-325 ◽  
pp. 1035-1038 ◽  
Author(s):  
Michihiro Sato ◽  
Tetsuya Ohashi ◽  
Takuya Maruizumi ◽  
Isao Kitagawa
Keyword(s):  
Crystal Plasticity ◽  
Thermal Deformation ◽  
Room Temperature ◽  
Friction Stress ◽  
High Temperature Region ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Half Loop ◽  
The Difference ◽  
Lattice Friction

Thermal stress, plastic slip deformation and accumulation of dislocations in shallow trench isolation (STI) type ULSI devices when the temperature drops from 1000 し to room temperature are analyzed by a crystal plasticity analysis cord. The results show that dislocation accumulation takes place at the temperature range over 800 し, and the difference of 6 MPa in the lattice friction stress at 1000 し!causes increase of dislocation density more than 1.6 times. Dislocations generate and accumulate at the shoulder part of the device area and bottom corners of the trench. Dislocations are categorized into two groups. In one group, dislocation lines are mostly straight and parallel to the trench direction, and in the other group, dislocations make half loop type structure. Possibilities for the suppression of dislocation accumulation through control of lattice friction stress at high temperature region are discussed.

Bestimmung des zerebralen Blutflusses mittels des 81 Rb/81 mKr-Generatorsystems

1990 ◽  
Vol 29 (01) ◽  
pp. 7-12 ◽  
Author(s):  
J. Bialy ◽  
F.-J. Hans ◽  
E. Oberhausen ◽  
W.J. Peters ◽  
M. Schmitt ◽  
...  
Keyword(s):  
Blood Flow ◽  
Cerebral Blood Flow ◽  
Blood Circulation ◽  
Semiconductor Device ◽  
Animal Experiments ◽  
Initial Value ◽  
Brain Arteries ◽  
Sufficient Concentration ◽  
Static Quantity

A method is being developed which not only measures cerebral blood flow as a static quantity but also its changes with time. For that purpose a semiconductor device ascertains the proportion of intracerebral81 Rb and 81mKr activities. By opening the haemato-encephalic barrier in animal experiments a sufficient concentration of intracerebral81 Rb could be attained and the modified blood circulation after step-wise ligature of all brain arteries brought into relation to the corresponding Rb/Kr quotient. Over the range from undisturbed to completely interrupted cerebral blood flow this quotient varied up to 25% of its initial value.

Micro-Raman Spectroscopy Evaluation of the Local Mechanical Stress in Shallow Trench Isolation CMOS Structures: Correlation with Defect Generation and Diode Leakage

1998 ◽  
Author(s):  
I. De Wolf ◽  
G. Groeseneken ◽  
H.E. Maes ◽  
M. Bolt ◽  
K. Barla ◽  
...  
Keyword(s):  
Raman Spectroscopy ◽  
Mechanical Stress ◽  
Defect Formation ◽  
Active Area ◽  
Wet Oxidation ◽  
Leakage Currents ◽  
Shallow Trench Isolation ◽  
Micro Raman Spectroscopy ◽  
Silicon Devices ◽  
Trench Isolation

Abstract It is shown, using micro-Raman spectroscopy, that Shallow Trench Isolation introduces high stresses in the active area of silicon devices when wet oxidation steps are used. These stresses result in defect formation in the active area, leading to high diode leakage currents. The stress levels are highest near the outer edges of line structures and at square structures. They also increase with decreasing active area dimensions.

Advances in Chemical-Mechanical Planarization

MRS Bulletin ◽  
2002 ◽  
Vol 27 (10) ◽  
pp. 743-751 ◽  
Author(s):  
Rajiv K. Singh ◽  
Rajeev Bajaj
Keyword(s):  
Surface Topography ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Chemical Mechanical Planarization ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Fundamental Understanding ◽  
Copper Polishing ◽  
Future Growth

AbstractThe primary aim of this issue of MRS Bulletin is to present an overview of the materials issues in chemical–mechanical planarization (CMP), also known as chemical–mechanial polishing, a process that is used in the semiconductor industry to isolate and connect individual transistors on a chip. The CMP process has been the fastest-growing semiconductor operation in the last decade, and its future growth is being fueled by the introduction of copper-based interconnects in advanced microprocessors and other devices. Articles in this issue range from providing a fundamental understanding of the CMP process to the latest advancements in the field. Topics covered in these articles include an overview of CMP, fundamental principles of slurry design, understanding wafer–pad–slurry interactions, process integration issues, the formulation of abrasive-free slurries for copper polishing, understanding surface topography issues in shallow trench isolation, and emerging applications.

Non-Destructive Measurements of III-V Semiconductor Device Structure by a Hard X-ray Microprobe

1991 ◽  
Vol 240 ◽  
Author(s):  
F. Uchida ◽  
J. Shigeta ◽  
Y. SUZUKI
Keyword(s):  
Semiconductor Device ◽  
Film Structure ◽  
Device Structure ◽  
X Ray ◽  
Model Sample ◽  
Device Structures ◽  
The Difference ◽  
X Ray Absorption ◽  
Non Destructive ◽  
Non Destructive Characterization

ABSTRACTA non-destructive characterization technique featuring a hard X-ray Microprobe is demonstrated for lll-V semiconductor device structures. A GaAs FET with a 2 μm gate length is measured as a model sample of a thin film structure. X-ray scanning microscopic images of the FET are obtained by diffracted X-ray and fluorescence X-ray detection. Diffracted X-ray detection measures the difference in gate material and source or drain material as a gray level difference on the image due to the X-ray absorption ratio. Ni Ka fluorescence detection, on the other hand, provides imaging of 500 Å thick Ni layers, which are contained only in the source and drain metals, through non-destructive observation.

Analysis of Self-Heating Effects on vertical FET according to Shallow Trench Isolation

2017 ◽  
Vol 137 ◽  
pp. 123-127
Author(s):  
Ilho Myeong ◽  
Dokyun Son ◽  
Hyunsuk Kim ◽  
Myounggon Kang ◽  
Hyungcheol Shin
Keyword(s):  
Shallow Trench Isolation ◽  
Self Heating ◽  
Heating Effects ◽  
Trench Isolation
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