Impact of Threading Dislocations Detected by KOH Etching on 4H-SiC 650 V MOSFET Device Failure after Reliability Test

2020 ◽  
Vol 1004 ◽  
pp. 472-476
Author(s):  
Andrea Severino ◽  
Ruggero Anzalone ◽  
Nicolò Piluso ◽  
Elisa Vitanza ◽  
Beatrice Carbone ◽  
...  
Keyword(s):  
High Temperature ◽  
Wet Etching ◽  
Underlying Structure ◽  
Reliability Test ◽  
Defect Classification ◽  
Threading Dislocations ◽  
Dislocation Defects ◽  
Failure Location ◽  
Failure Site ◽  
Koh Etching

In this study, the correlation between the Emission Microscopy (Em.Mi.) related to the failure site of the 4H-SiC 650V MOSFET devices after reliability test and epitaxial dislocation defects is presented. Devices failed at the High-Temperature Reverse Bias (HTRB) test were considered. Device layers have been stripped out by chemical wet etching and etched in a high temperature KOH solution to characterize defects emerging at the SiC surface. This approach was used to correlate failure emission spots with underlying structure of the material. KOH etching process on delayered devices was performed at 500°C for 10 minutes and then analysis by optical microscopy and SEM was carried out for defect classification and correlation with failure location.

First Demonstration of High Temperature SiC CMOS Gate Driver in Bridge Leg for Hybrid Power Module Application

2018 ◽  
Vol 924 ◽  
pp. 854-857
Author(s):  
Ming Hung Weng ◽  
Muhammad I. Idris ◽  
S. Wright ◽  
David T. Clark ◽  
R.A.R. Young ◽  
...  
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Initial Increase ◽  
Reliability Test ◽  
Power Devices ◽  
Power Module ◽  
Hybrid Power ◽  
Gate Driver ◽  
Passive Circuit

A high-temperature silicon carbide power module using CMOS gate drive technology and discrete power devices is presented. The power module was aged at 200V and 300 °C for 3,000 hours in a long-term reliability test. After the initial increase, the variation in the rise time of the module is 27% (49.63ns@1,000h compared to 63.1ns@3,000h), whilst the fall time increases by 54.3% (62.92ns@1,000h compared to 97.1ns@3,000h). The unique assembly enables the integrated circuits of CMOS logic with passive circuit elements capable of operation at temperatures of 300°C and beyond.

Removal of Mechanical-Polishing-Induced Surface Damages on 4H-SiC by Chemical Etching and its Effect on Subsequent Epitaxial Growth

2015 ◽  
Vol 821-823 ◽  
pp. 541-544 ◽  
Author(s):  
Yong Zhao Yao ◽  
Yukari Ishikawa ◽  
Yoshihiro Sugawara ◽  
Koji Sato
Keyword(s):  
High Temperature ◽  
Epitaxial Growth ◽  
Chemical Etching ◽  
Flat Surface ◽  
Mechanical Polishing ◽  
Wet Etching ◽  
Surface Damages

To remove the surface damages induced during mechanical polishing (MP) of 4H-SiC, a variety of wet etching recipes and etching conditions were studied. By evaluating the epilayers grown on these etching-treated wafers, it has been found that triangular defects (TRDs) are the main defects originated from the MP-induced damages in these samples. High temperature molten KCl etching at 1100 °C with KOH additive is very effective to remove the damaged surface while keeping a relatively flat surface. Epilayer grown on the KCl+KOH etched wafer showed a TRD density <0.9 cm-2.

Microlithography of high-temperature superconducting films: laser ablation vs. wet etching

1989 ◽  
Vol 25 (2) ◽  
pp. 950-953 ◽  
Author(s):  
P.H. Ballentine ◽  
A.M. Kadin ◽  
M.A. Fisher ◽  
D.S. Mallory ◽  
W.R. Donaldson
Keyword(s):  
High Temperature ◽  
Laser Ablation ◽  
Superconducting Films ◽  
Wet Etching ◽  
High Temperature Superconducting

Topology Optimization of Micromachined Structures With the Manufacturing Constraints of KOH Etching of (110) Silicon

2008 ◽  
Author(s):  
Sudarshan Hegde ◽  
G. K. Ananthasuresh
Keyword(s):  
Topology Optimization ◽  
Aspect Ratio ◽  
High Aspect Ratio ◽  
Cost Effective ◽  
Wet Etching ◽  
Minimum Length ◽  
The Cost ◽  
Design Parameterization ◽  
Koh Etching ◽  
Si Wafer

The focus of this paper is on designing useful compliant micro-mechanisms of high-aspect-ratio which can be microfabricated by the cost-effective wet etching of (110) orientation silicon (Si) wafers. Wet etching of (110) Si imposes constraints on the geometry of the realized mechanisms because it allows only etch-through in the form of slots parallel to the wafer’s flat with a certain minimum length. In this paper, we incorporate this constraint in the topology optimization and obtain compliant designs that meet the specifications on the desired motion for given input forces. Using this design technique and wet etching, we show that we can realize high-aspect-ratio compliant micro-mechanisms. For a (110) Si wafer of 250 μm thickness, the minimum length of the etch opening to get a slot is found to be 866 μm. The minimum achievable width of the slot is limited by the resolution of the lithography process and this can be a very small value. This is studied by conducting trials with different mask layouts on a (110) Si wafer. These constraints are taken care of by using a suitable design parameterization rather than by imposing the constraints explicitly. Topology optimization, as is well known, gives designs using only the essential design specifications. In this work, we show that our technique also gives manufacturable mechanism designs along with lithography mask layouts. Some designs obtained are transferred to lithography masks and mechanisms are fabricated on (110) Si wafers.

BPD-TED Conversion in the SiC Substrate after High-Temperature Si-VE

2020 ◽  
Vol 1004 ◽  
pp. 401-407
Author(s):  
Yusuke Sudoh ◽  
Makoto Kitabatake ◽  
Tadaaki Kaneko
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Chemical Etching ◽  
Surface Region ◽  
Etching Process ◽  
Koh Etching

We propose the Si-Vapor Etching (Si-VE), which is thermal chemical etching process, as epi-ready treatment for Silicon Carbide (SiC). In this work, we report the evaluation results of BPD-TED conversion by Si-VE treatment using repeated KOH etching process. This method makes it possible to observe BPD-TED conversion in a very shallow surface region of the SiC substrate. 80% of BPDs is converted to TEDs with a depth of more than 80nm under optimized Si-VE 2000°C conditions. Furthermore, 53% of BPDs were converted to TEDs with 140nm or more depth, which has been confirmed under optimized 1800°C Si-VE conditions.

Reliability Test Integrating Electrical and Mechanical Stress at High Temperature for a-InGaZnO Thin Film Transistors

2019 ◽  
Vol 19 (2) ◽  
pp. 433-436 ◽  
Author(s):  
Yu-Ching Tsao ◽  
Ting-Chang Chang ◽  
Shin-Ping Huang ◽  
Yu-Lin Tsai ◽  
Yu-Chieh Chien ◽  
...  
Keyword(s):  
Thin Film ◽  
High Temperature ◽  
Mechanical Stress ◽  
Thin Film Transistors ◽  
Reliability Test

Strategies for Defect-Free and Deep Wet Etching of Pyrex 7740

2015 ◽  
Vol 645-646 ◽  
pp. 21-25
Author(s):  
Zhan Zhan ◽  
Ling Ke Yu ◽  
Cheng Zheng ◽  
Jian Fa Cai ◽  
Dao Heng Sun ◽  
...  
Keyword(s):  
High Temperature ◽  
Wet Etching ◽  
Pyrex Glass ◽  
Solution Component ◽  
Etched Surface ◽  
20 Nm ◽  
Glass Etching ◽  
Pyrex 7740

In this paper, two aspects in the wet glass etching, the pre-annealing of the glass and the mask process, are taken into consideration to achieve the deep and defect-free wet etching of Pyrex glass. Compared with the conventional strategies, i.e.,HFsolution component and mask kinds, our experiment results prove the pre-annealing is another key role to obtain theoretical isotropy character in wet etching. Besides, the high temperature pre-annealing dramatically improves the structure profiles and reduces the notching defects. Additionally, a novel multilayer mask process is proposed. With 1.5μmPR/ 100nmAu/ 100 nmAu/ 20 nmCrmask and > 450 °C pre-annealing, > 150 μm deep and non-pin-holes Pyrex glass structures are achieved and the roughness of etched surface is lower than 1 nm.

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