Channel Hot-Carrier Effect of 4H-SiC MOSFET

2009 ◽  
Vol 615-617 ◽  
pp. 813-816 ◽  
Author(s):  
Liang Chun Yu ◽  
Kin P. Cheung ◽  
John S. Suehle ◽  
Jason P. Campbell ◽  
Kuang Sheng ◽  
...  

SiC MOSFET, as power device, can be expected to operate with high drain and high gate voltages, possibly leading to hot-carrier effect. However, hot-carrier degradation in a SiC MOSFET is difficult to detect because the as fabricated devices contain high level of defects. We report, for the first time, evidence of hot-carrier effect in 4H-SiC MOSFET. The result suggests that hot hole from impact ionization trapped in the oxide is the cause of the channel hot-carrier effect.

1998 ◽  
Vol 544 ◽  
Author(s):  
Y. J. Seo ◽  
W. S. Choi ◽  
S. Y. Kim ◽  
C. I. Kim ◽  
E. G. Chang ◽  
...  

AbstractIt is very important to select superior interlayer Pre Metal Dielectric (PMD) materials which can act as a penetration barrier to various impurities created by the Chemical Mechanical Polishing (CMP) processes. In this paper, hot carrier degradation and device characteristics were investigated with material variation of PMD-1 layers, which were split by LP-TEOS, SR-oxide, PE-oxynitride, PE-nitride and PE-TEOS films. It was observed that the PE-oxynitride and PEnitride using plasma was greatly deteriorated in hot carrier effect in comparison with silicon oxide. Consequently, it is clearly shown that silicon oxide turned out to be a better PMD-1 material than both PE-oxynitride and PE-nitride. From the results, it is suggested that LP-TEOS film is the best PMD-1 material among the silicon oxide samples.


1995 ◽  
Vol 391 ◽  
Author(s):  
S. Saha ◽  
C. S. Yeh ◽  
Ph. Lindorfer ◽  
J. Luo ◽  
U. Nellore ◽  
...  

AbstractThis paper describes an application of process and device simulation programs in the study of substrate current generated by hot-carrier effect in submicron p-channel MOSFET devices. The impact ionization model for holes was calibrated for accurate simulation of substrate current in submicron devices, and an expression for the impact ionization rate of holes in silicon is obtained. The simulated substrate current for 0.57, 0.73 and 1.13 μm devices obtained by the optimized expression agrees very well with the measured data. The optimized impact ionization expression was also used to simulate the effect of p- Lightly Doped Drain impurity profile on substrate current, and the simulated peak substrate current and the corresponding maximum lateral channel electric field as a function of p- dose and length are presented.


1986 ◽  
Vol 33 (3) ◽  
pp. 424-426 ◽  
Author(s):  
Kueing-Long Chen ◽  
S. Saller ◽  
R. Shah

Author(s):  
Jiangwei Cui ◽  
Qiwen Zheng ◽  
Bingxu Ning ◽  
Xuefeng Yu ◽  
Kai Zhao ◽  
...  

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