Hot-Carrier Effect in Submicron pMOSFETs

1995 ◽  
Vol 391 ◽  
Author(s):  
S. Saha ◽  
C. S. Yeh ◽  
Ph. Lindorfer ◽  
J. Luo ◽  
U. Nellore ◽  
...  

AbstractThis paper describes an application of process and device simulation programs in the study of substrate current generated by hot-carrier effect in submicron p-channel MOSFET devices. The impact ionization model for holes was calibrated for accurate simulation of substrate current in submicron devices, and an expression for the impact ionization rate of holes in silicon is obtained. The simulated substrate current for 0.57, 0.73 and 1.13 μm devices obtained by the optimized expression agrees very well with the measured data. The optimized impact ionization expression was also used to simulate the effect of p- Lightly Doped Drain impurity profile on substrate current, and the simulated peak substrate current and the corresponding maximum lateral channel electric field as a function of p- dose and length are presented.

2020 ◽  
Vol 34 (12) ◽  
pp. 2050119
Author(s):  
Meng Zhang ◽  
Ruohe Yao

With the development of IC manufacturing process, the device dimensions have been on the nanoscale, while the device performance, such as the electron velocity, mobility and thermal noise, is significantly affected by the hot carrier effect. This paper proposes an electron temperature model to accurately predict the hot carrier effect. The channel transverse electric field is firstly derived by using the channel electric potential equation, taking into account the boundary conditions of the electric field. Based on the electric field equation, the energy balance equation is solved involving the impact of the temperature gradient and then the electron temperature model is established. The impact of the electron temperature on the channel mobility and of temperature gradient on the electron velocity has also been investigated. The results show that when the device enters the nanoscale, the electron mobility is more susceptible to the influence of the electric field and the electron temperature, and the impact of the temperature gradient on the velocity becomes obviously greater. The electron temperature model proposed in this paper can be applied to the performance analysis and modeling of nanosized MOSFETs.


1979 ◽  
Vol 55 (1) ◽  
pp. 197-202 ◽  
Author(s):  
Z. Dobrovolskis ◽  
W. Hoerstel ◽  
A. Krotkus

2009 ◽  
Vol 615-617 ◽  
pp. 813-816 ◽  
Author(s):  
Liang Chun Yu ◽  
Kin P. Cheung ◽  
John S. Suehle ◽  
Jason P. Campbell ◽  
Kuang Sheng ◽  
...  

SiC MOSFET, as power device, can be expected to operate with high drain and high gate voltages, possibly leading to hot-carrier effect. However, hot-carrier degradation in a SiC MOSFET is difficult to detect because the as fabricated devices contain high level of defects. We report, for the first time, evidence of hot-carrier effect in 4H-SiC MOSFET. The result suggests that hot hole from impact ionization trapped in the oxide is the cause of the channel hot-carrier effect.


2001 ◽  
Vol 24 (2) ◽  
pp. 129-134
Author(s):  
Y. Amhouche ◽  
A. El Abbassi ◽  
K. Raïs ◽  
E. Bendada ◽  
R. Rmaily

A new method for drain saturation voltage extraction in submicron MOSFETs is presented. It is based on measurements of the partial derivative of the impact ionization rate. The method has been tested using main of channel length MOSFET devices and compared with others methods.


2020 ◽  
Vol 1004 ◽  
pp. 998-1003
Author(s):  
Jia Xing Wei ◽  
Si Yang Liu ◽  
Sheng Li ◽  
Li Zhi Tang ◽  
Rong Cheng Lou ◽  
...  

The unexpected resistance reduction effect of double-trench SiC MOSFETs under repetitive avalanche stress is investigated in this work. After enduring repetitive avalanche stress, the ON-state drain-source resistance (Rdson) of the device decreases. With the help of TCAD simulations, the dominant mechanism is proved to be the injection of positive charges into the gate trench bottom oxide, which is almost irreversible under zero-voltage bias condition at room temperature. For the injected positive charges attract extra electrons just beneath the gate trench bottom, where the carriers pass through under ON state, the resistivity there is reduced, improving the conduction capability of the device. Moreover, an optimization method is proposed. Since the impact ionization rate (I.I.) and the vertical oxide electric field (E⊥) along the gate trench bottom oxide interface contribute to the injection of positive charges, it is recommended to make the bottom oxide thicker to suppress this effect.


2000 ◽  
Vol 87 (2) ◽  
pp. 781-788 ◽  
Author(s):  
R. Redmer ◽  
J. R. Madureira ◽  
N. Fitzer ◽  
S. M. Goodnick ◽  
W. Schattke ◽  
...  

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