Influence of Annealing Parameters on Surface Roughness, Mobility and Contact Resistance of Aluminium Implanted 4H SiC

2011 ◽  
Vol 679-680 ◽  
pp. 417-420
Author(s):  
H. Schmitt ◽  
Volker Haeublein ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
Surface Roughness ◽  
Contact Resistance ◽  
Carrier Mobility ◽  
Annealing Process ◽  
Specific Contact Resistance ◽  
High Dose ◽  
Capping Layer ◽  
Implantation Temperature ◽  
Specific Contact ◽  
The Impact

The impact of implantation temperature and dose as well as the annealing process with and without a graphite capping layer on surface roughness, carrier mobility and specific contact resistance are investigated and compared. The use of the capping layer is proven to be particularly advantageous: (1) a deterioration of surface roughness can be avoided even for high dose implantations and (2) the specific contact resistance is reduced. Furthermore, it is shown that a capping layer prevents surface contamination during annealing.

scholarly journals Comparison of Electrical Properties of Ohmic Contact Realized on p-Type 4H-SiC

2008 ◽  
Vol 600-603 ◽  
pp. 639-642
Author(s):  
Duy Minh Nguyen ◽  
Christophe Raynaud ◽  
Mihai Lazar ◽  
Heu Vang ◽  
Dominique Planson
Keyword(s):  
Surface Roughness ◽  
Electrical Properties ◽  
Contact Resistance ◽  
Carrier Mobility ◽  
Ohmic Contacts ◽  
Series Resistance ◽  
Specific Contact Resistance ◽  
Specific Contact ◽  
P Type ◽  
Post Implantation

N+ 4H-SiC commercial substrates with n-type epilayers have been used to realize bipolar diodes and TLM structures. The p-type emitter of diodes was realized by Al implantations followed by a post-implantation annealing with or without a graphite capping layer. Ohmic contacts were formed by depositing Ti/Ni on the backside and Ni/Al on the topside of the wafer. It appears that capping the sample during the annealing reduces considerably the surface roughness and the specific contact resistance. Sheet resistance and specific contact resistance as low as 2kΩ/□ and respectively 1.75×10-4 Ωcm² at 300 K have been obtained. I-V measurements as a function of temperature have been performed from ~100 to ~500 K. The variations of the series resistance vs. temperature can be explained by the freeze-out of carriers and by the variation of carrier mobility.

TiW/TiWN/Pt Ohmic Contacts to n-Type 3C-SiC

2006 ◽  
Vol 911 ◽  
Author(s):  
Kirk Hofeling ◽  
Loren Rieth ◽  
Florian Solzbacher
Keyword(s):  
Contact Resistance ◽  
Room Temperature ◽  
Ohmic Contacts ◽  
Specific Contact Resistance ◽  
Test Duration ◽  
Capping Layer ◽  
Interface Reactions ◽  
Transmission Line Method ◽  
Specific Contact

AbstractTiW(40 nm)/TiWN(80 nm)/Pt(500nm) was investigated as a new high-temperature compatible contact stack to 3C-SiC for harsh environment applications. Performance of TiW/TiWN/Pt contacts deposited on unintentionally doped (8.85×1018 cm-3) 3C-SiC grown by LPCVD to a thickness of ~1μm on (100) Si are reported. The linear transmission line method was used to determine specific contact resistance (ρc) at room temperature and for long-term tests at 300 °C. As deposited contacts were Ohmic with a ρc range of 1×10-4 to 1×10-3 cm2. These contacts were annealed for five minutes in forming gas (8% H2 92% Ar), at temperatures from 450 to 950 °C and all retained Ohmic character. Annealing samples at 450, 550 and 950 °C decreased ρc while anneling between 650 and 850 °C generally increased ρc.Auger Electron Spectroscopy (AES) analysis was performed on a sample annealed at 750 °C. The as-received surface was composed of Si and O; after a brief sputter etch a characteristic Pt peak became visible and the O peak decreased substantially. Depth profiles detected Si throughout the Pt capping layer but not in the TiW layers. We suspect that Si diffuses from the SiC substrate into the Pt capping layer and surface Si also reacts with O2 to from an oxide. These reactions, in combination with incomplete SiC/TiW interface reactions, are suspected to cause the increase of ρc for samples annealed between 650 and 850 °C. Annealing at 950 °C gave the lowest contact resistance of 2.3×10-5. Long-term testing at 300 °C for 190 hours, in atmosphere, was performed on contacts annealed at 450 °C. When heated, the contacts initial ρc of 2.1×10-4 cm2 increased to ~4×10-3 cm2 which remained stable for the test duration. After long-term testing the sample ρc measured at room temperature decreased to 9.8×10-5 cm2.

Impact of Surface Morphology on the Electrical Properties of Al/Ti Ohmic Contacts on Al-Implanted 4H-SiC

2011 ◽  
Vol 679-680 ◽  
pp. 413-416
Author(s):  
Alessia Frazzetto ◽  
Fabrizio Roccaforte ◽  
Filippo Giannazzo ◽  
Raffaella Lo Nigro ◽  
Corrado Bongiorno ◽  
...  
Keyword(s):  
Surface Roughness ◽  
Electrical Properties ◽  
Surface Morphology ◽  
Ohmic Contacts ◽  
Metal Layer ◽  
Morphological Data ◽  
Specific Contact Resistance ◽  
Interfacial Region ◽  
Specific Contact ◽  
The Impact

This paper reports on the impact of the surface morphology on the properties of Ti/Al Ohmic contacts fabricated on Al-implanted 4H-SiC. In particular, the surface roughness of the Al-implanted regions after annealing at 1700 °C was strongly reduced by the using a protective carbon capping layer during annealing (the surface roughness decreased from 9.0 nm to 1.3 nm). In this way, also the morphology and the specific contact resistance of Ti/Al Ohmic contacts formed on the implanted regions could be improved. The electrical and morphological data were correlated with the structural properties of the reacted metal layer and of the metal/SiC interfacial region.

Ohmic Contact on n-Type 3C-SiC Activated with SiO2 Encapsulation

2015 ◽  
Vol 821-823 ◽  
pp. 395-398
Author(s):  
Fan Li ◽  
Yogesh Sharma ◽  
Dean Hamilton ◽  
Craig Fisher ◽  
Mike Jennings ◽  
...  
Keyword(s):  
Surface Roughness ◽  
Annealing Process ◽  
Influential Factors ◽  
Specific Contact Resistance ◽  
Semiconductor Surface ◽  
Si Substrate ◽  
Surface Protection ◽  
Specific Contact ◽  
Activation Annealing ◽  
Post Implantation

This work has focused on using a deposited SiO2layer as the surface protection for 3C-SiC post-implantation activation annealing process. The 3C-SiC epilayers are grown on a Si substrate, nitrogen implanted and then annealed. Both physical and electrical characterisation tools are used to evaluate the influential factors, including implantation doses, semiconductor surface roughness and post-implantation anneal conditions. It is found out that, the SiO2capped samples achieved lower specific contact resistance in highest temperature conditions. The lowest contact resistivity of the SiO2capped sample is 4.9x10-6Ω.cm2, which is 65.4% lower than the unprotected sample annealed in the same condition.

Improvement of the Specific Contact Resistance on P-Type 4H-SiC by Using a Highly P-Typed Doped 4H-SiC Layer Selectively Grown by VLS Transport

2014 ◽  
Vol 806 ◽  
pp. 57-60
Author(s):  
Nicolas Thierry-Jebali ◽  
Arthur Vo-Ha ◽  
Davy Carole ◽  
Mihai Lazar ◽  
Gabriel Ferro ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Ohmic Contacts ◽  
Schottky Barrier Height ◽  
Annealing Temperature ◽  
Process Condition ◽  
Specific Contact Resistance ◽  
High Doping Level ◽  
Annealing Temperatures ◽  
Specific Contact ◽  
P Type

This work reports on the improvement of ohmic contacts made on heavily p-type doped 4H-SiC epitaxial layer selectively grown by Vapor-Liquid-Solid (VLS) transport. Even before any annealing process, the contact is ohmic. This behavior can be explained by the high doping level of the VLS layer (Al concentration > 1020 cm-3) as characterized by SIMS profiling. Upon variation of annealing temperatures, a minimum value of the Specific Contact Resistance (SCR) down to 1.3x10-6 Ω.cm2 has been obtained for both 500 °C and 800 °C annealing temperature. However, a large variation of the SCR was observed for a same process condition. This variation is mainly attributed to a variation of the Schottky Barrier Height.

Current Transport in Ti/Al/Ni/Au Ohmic Contacts to GaN and AlGaN

2007 ◽  
Vol 556-557 ◽  
pp. 1027-1030 ◽  
Author(s):  
Ferdinando Iucolano ◽  
Fabrizio Roccaforte ◽  
Filippo Giannazzo ◽  
A. Alberti ◽  
Vito Raineri
Keyword(s):  
Contact Resistance ◽  
Field Emission ◽  
Ohmic Contacts ◽  
Theoretical Models ◽  
Specific Contact Resistance ◽  
Strong Increase ◽  
Current Transport ◽  
Electrical Characteristics ◽  
Structural And Electrical Properties ◽  
Specific Contact

In this work, the structural and electrical properties of Ti/Al/Ni/Au contacts on n-type Gallium Nitride were studied. An ohmic behaviour was observed after annealing above 700°C. The structural analysis showed the formation of an interfacial TiN layer and different phases in the reacted layer (AlNi, AlAu4, Al2Au) upon annealing. The temperature dependence of the specific contact resistance demonstrated that the current transport occurs through thermoionic field emission in the contacts annealed at 600°C, and field emission after annealing at higher temperatures. By fitting the data with theoretical models, a reduction of the Schottky barrier from 1.21eV after annealing at 600°C to 0.81eV at 800°C was demonstrated, together with a strong increase of the carrier concentration at the interface. The reduction of the contact resistance upon annealing was discussed by correlating the structural and electrical characteristics of the contacts.

Modelling Geometrical Effects of Parasitic and Contact Resistance of FET Devices

1996 ◽  
Vol 427 ◽  
Author(s):  
Geoffrey K. Reeves ◽  
H. Barry Harrison ◽  
Patrick W. Leech
Keyword(s):  
Contact Resistance ◽  
Material Properties ◽  
Ohmic Contacts ◽  
Difficult Problem ◽  
Specific Contact Resistance ◽  
Metal Silicide ◽  
Transmission Line Model ◽  
Specific Contact ◽  
Geometrical Effects ◽  
Contact Parameters

AbstractThe continual trend in decreasing the dimensions of semiconductor devices results in a number of technological problems. One of the more significant of these is the increase in contact resistance, Rc. In order to understand and counteract this increase, Rc needs to be quantitatively modelled as a function of the geometrical and material properties of the contact. However the use of multiple semiconductor layers for ohmic contacts makes the modelling and calculation of Rc a more difficult problem. In this paper, a Tri-Layer Transmission Line Model (TLTLM) is used to analyse a MOSFET ohmic contact and gatedrain region. A quantitative assessment of the influence on Rc of important contact parameters such as the metal-silicide specific contact resistance, the silicide-silicon specific contact resistance and the gate-drain length can thus be made. The paper further describes some of the problems that may be encountered in defining Rc when the dimensions of certain types of contact found in planar devices decrease.

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