Carrier Lifetimes in 4H-SiC Epitaxial Layers on the C-Face Enhanced by Carbon Implantation

2018 ◽  
Vol 924 ◽  
pp. 432-435 ◽  
Author(s):  
Mitsuhiro Kushibe ◽  
Johji Nishio ◽  
Ryosuke Iijima ◽  
Akira Miyasaka ◽  
Hirokuni Asamizu ◽  
...  

Carrier lifetime in low carrier concentration 4H-SiC epitaxial layers grown on the C-face was enhanced by using carbon implantation and post annealing. The measured carrier lifetime increased with the thickness of the epitaxial layer and was 11.4 µs for the 150 µm thick epitaxial layer. The internal carrier lifetime was estimated as 21 µs from the dependence of the measured carrier lifetime on the epitaxial layer thickness. This value is almost comparable to the reported values of the internal carrier lifetime for the layers grown on the Si-face.

2006 ◽  
Vol 527-529 ◽  
pp. 159-162 ◽  
Author(s):  
Albert A. Burk ◽  
Michael J. O'Loughlin ◽  
Michael J. Paisley ◽  
Adrian R. Powell ◽  
M.F. Brady ◽  
...  

Experimental results are presented for SiC epitaxial layer growth employing a large-area, up to 8x100-mm, warm-wall planetary SiC-VPE reactor. This high-throughput reactor has been optimized for the growth of uniform 0.01 to 80-micron thick, specular, device-quality SiC epitaxial layers with low background doping concentrations of <1x1014 cm-3 and intentional p- and n-type doping from ~1x1015 cm-3 to >1x1019 cm-3. Intrawafer layer thickness and n-type doping uniformity (σ/mean) of ~2% and ~8% have been achieved to date in the 8x100-mm configuration. The total range of the average intrawafer thickness and doping within a run are approximately ±1% and ±6% respectively.


2014 ◽  
Vol 778-780 ◽  
pp. 214-217 ◽  
Author(s):  
Kentaro Tamura ◽  
Chiaki Kudou ◽  
Keiko Masumoto ◽  
Johji Nishio ◽  
Kazutoshi Kojima

We have grown epitaxial layers on 2° off-cut 4H-SiC(0001) Si-face substrates. The epitaxial layer surfaces on 2° off-cut substrates are more prone to generate step-bunching than on 4° off-cut substrates, which are observed by confocal microscopy with differential interference contrast. We have speculated that the step-bunching is generated at the beginning of an epitaxial growth. Triangular defect density of epitaxial layers on 2° off-cut substrates is as low as 0.7 cm–2 for the size corresponding to 150 mm. We have firstly reported distribution of 2° off-cut epitaxial layers for the 150-mm size using two 76.2-mm wafers: σ/mean = 3.3% for thickness, σ/mean = 7.3% for carrier concentration.


1993 ◽  
Vol 311 ◽  
Author(s):  
Alexander L. Roytburd

ABSTRACTThe effect of the elastic energy of internal stresses in a system of coherent phases within an epitaxial layer is considered. The equilibrium two-phase layer has a transversely modulated structure with a modulation period dependent on the layer thickness. The phase diagrams for the phases in an epitaxial layer can differ qualitatively from standard phase diagrams, and this difference also depends on the layer thickness.


2007 ◽  
Vol 556-557 ◽  
pp. 57-60
Author(s):  
James D. Oliver ◽  
Brian H. Ponczak

A series of designed experiments have been conducted over a period of years in a multiwafer, planetary rotation, epitaxial reactor to quantify the effects of various epitaxial growth process parameters on the resulting SiC epitaxial layers. This paper summarizes the results obtained through statistically designed experiments varying process parameters and their resultant effect on the layer thickness, carrier concentration and the variability of these parameters wafer-to-wafer, and within a wafer.


2007 ◽  
Vol 556-557 ◽  
pp. 153-156
Author(s):  
Chi Kwon Park ◽  
Gi Sub Lee ◽  
Ju Young Lee ◽  
Myung Ok Kyun ◽  
Won Jae Lee ◽  
...  

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. In this study, we aimed to systematically investigate surface morphologies and electrical properties of SiC epitaxial layers grown with varying a SiC/Al ratio in a SiC source powder during the sublimation growth using the CST method. It was confirmed that the acceptor concentration of epitaxial layer was continuously decreased with increasing the SiC/Al ratio. The blue light emission was successfully observed on a PN diode structure fabricated with the p-type SiC epitaxial layer. Furthermore, 4H-SiC MESFETs having a micron-gate length were fabricated using a lithography process and their current-voltage performances were characterized.


2017 ◽  
Vol 897 ◽  
pp. 287-290 ◽  
Author(s):  
Matthias Kocher ◽  
Michael Niebauer ◽  
Mathias Rommel ◽  
Volker Haeublein ◽  
Anton J. Bauer

Point contact current voltage (PCIV) measurements were performed on 4H-SiC samples, both for n- an p-doped epitaxial layers as well as samples with rather shallow doping profiles realized by N- or Al-implantation in a range from 1016 cm-3 to 1019 cm-3. Surface preparation and measurement parameters were investigated in order to determine their influence on the measured resistance profiles. Furthermore depth profile measurements were performed on both an epitaxial layer as well as on implanted samples. These depth profiles could be measured reproducibly and showed good agreement with expected profiles for Al-implanted samples as well as for epitaxial layer whereas for N-implanted samples deviations between measured and expected profiles could be observed. It could be proven that PCIV profiling technique is a promising method for characterizing doped profiles in 4H-SiC, especially on Al-implanted samples.


AIP Advances ◽  
2012 ◽  
Vol 2 (1) ◽  
pp. 012177 ◽  
Author(s):  
Yoshinobu Aoyagi ◽  
Misaichi Takeuchi ◽  
Sohachi Iwai ◽  
Hideki Hirayama

2019 ◽  
Vol 963 ◽  
pp. 399-402 ◽  
Author(s):  
Cristiano Calabretta ◽  
Massimo Zimbone ◽  
Eric G. Barbagiovanni ◽  
Simona Boninelli ◽  
Nicolò Piluso ◽  
...  

In this work, we have studied the crystal defectiveness and doping activation subsequent to ion implantation and post-annealing by using various techniques including photoluminescence (PL), Raman spectroscopy and transmission electron microscopy (TEM). The aim of this work was to test the effectiveness of double step annealing to reduce the density of point defects generated during the annealing of a P implanted 4H-SiC epitaxial layer. The outcome of this work evidences that neither the first 1 hour isochronal annealing at 1650 - 1700 - 1750 °C, nor the second one at 1500 °C for times between 4 hour and 14 hour were able to recover a satisfactory crystallinity of the sample and achieve dopant activations exceeding 1%.


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