Study of Etchants’ Diffusion into a 248 nm Deep UV Photoresist during a Wet Etch

2014 ◽  
Vol 219 ◽  
pp. 183-186 ◽  
Author(s):  
Mathieu Foucaud ◽  
Névine Rochat ◽  
Philippe Garnier ◽  
Erwine Pargon ◽  
Raluca Tiron
Keyword(s):  
Integrated Circuits ◽  
Plasma Etching ◽  
Chemical Etching ◽  
Carrier Mobility ◽  
Diffusion Rate ◽  
Material Interface ◽  
Surface Degradation ◽  
Surface Smoothness ◽  
Deep Uv ◽  
Wet Etch

Chemical etching is still preferred to plasma etching in numerous integrated circuits manufacturing steps. Indeed, it enables a better surface smoothness control, which is critical to obtain sufficient carrier mobility. During these steps, photoresist patterns protect underlying materials from etching. It is therefore mandatory to: 1) guarantee photoresist adhesion and keep patterns from being etched away; and 2) prevent surface degradation from etchants penetration down to the photoresist / material interface. To avoid this latter phenomenon, it is therefore crucial to know if etchants penetrate into the photoresist, and at which diffusion rate.

Surface Preparations Impact on 248nm Deep UV Photo Resists Adhesion during a Wet Etch

2012 ◽  
Vol 195 ◽  
pp. 58-61 ◽  
Author(s):  
Mathieu Foucaud ◽  
Philippe Garnier ◽  
Vincent Joseph ◽  
Erwine Pargon ◽  
Névine Rochat ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Plasma Etching ◽  
Integration Scheme ◽  
Metal Gate ◽  
Covalent Bonds ◽  
Gate Oxides ◽  
Process Step ◽  
High K ◽  
Lift Off ◽  
Wet Etch

Integrated circuits manufacturing still requires several wet etching operations in presence of photo resist. They are usually used to define the gate oxides or metal in a high k metal gate, gate first integration scheme. During this process step, the resist is used for masking and prevents the underneath material from being etched away. Wet treatments are preferred to plasma etching to perform this operation. Indeed, a smooth channels surface is mandatory to obtain a high carriers mobility. It is then critical to avoid any resist lift-off during the wet treatment in order to guarantee the underlying layers integrity. The observation of the lift-off phenomenon (figure 1) points out two possible root causes: 1) a lateral degradation of the covalent bonds at the interface between the polymer and the underlying material, and 2) a vertical resist degradation, due to the penetration of the etching chemicals into the resist down to the underlying material. Previous observations tend to link the lift-off severity to the bake temperature and the oxidation state of the surface on which the resist is coated.

Chemical Infiltration through Deep UV Photoresist

2016 ◽  
Vol 255 ◽  
pp. 117-121 ◽  
Author(s):  
Philippe Garnier ◽  
Marc Neyens
Keyword(s):  
Integrated Circuits ◽  
Performance Improvement ◽  
Gate Oxide ◽  
Clear Understanding ◽  
Optical Performance ◽  
Wet Chemical ◽  
Deep Uv ◽  
Wet Etch ◽  
Chemical Etchant ◽  
Positive Resist

Still nowadays in integrated circuits manufacturing, few materials patterns are defined by a wet etch on patterned deep UV photoresist. From dies to dies generation, an optical performance improvement is required, hence an evolution with thinner and thinner positive resist. This makes these latter more sensitive to wet chemical etchant through the polymer, reducing their protection of the underneath material. Following characterizations enable a clear understanding of BHF (Buffered HF) benefits versus diluted HF during a gate oxide definition.

Using the secondary electrons (SE) of SEM with NIST‘s MONSEL-II program to obtain improved linewidth measurements and slope angles of line edges on a MMIC GaAs device

1996 ◽  
Vol 54 ◽  
pp. 944-945
Author(s):  
Richard G. Sartore
Keyword(s):  
Integrated Circuits ◽  
Plasma Etching ◽  
Microwave Integrated Circuits ◽  
Monolithic Microwave Integrated Circuits ◽  
Thick Gold ◽  
Gaas Devices ◽  
Source Distance ◽  
Margin Of Error ◽  
Dimensional Measurements ◽  
Barrier Metal

In the evaluation of GaAs devices from the MMIC (Monolithic Microwave Integrated Circuits) program for Army applications, there was a requirement to obtain accurate linewidth measurements on the nominal 0.5 micrometer gate lengths used to fabricate these devices. Preliminary measurements indicated a significant variation (typically 10 % to 30% but could be more) in the critical dimensional measurements of the gate length, gate to source distance and gate to drain distance. Passivation introduced a margin of error, which was removed by plasma etching. Additionally, the high aspect ratio (4-5) of the thick gold (Au) conductors also introduced measurement difficulties. The final measurements were performed after the thick gold conductor was removed and only the barrier metal remained, which was approximately 250 nanometer thick platinum on GaAs substrate. The thickness was measured using the penetration voltage method. Linescan of the secondary electron signal as it scans across the gate is shown in Figure 1.

Metal-Assisted Plasma Etching of Silicon: A Liquid-Free Alternative to MACE

2018 ◽  
Author(s):  
Julia Sun ◽  
Benjamin Almquist
Keyword(s):  
Liquid Phase ◽  
Plasma Etching ◽  
Chemical Etching ◽  
Gold Films ◽  
Metallic Films ◽  
Au Catalyst ◽  
Feed Concentration ◽  
Catalytic Activities ◽  
Metal Assisted Chemical Etching ◽  
Complex Nanostructures

For decades, fabrication of semiconductor devices has utilized well-established etching techniques to create complex nanostructures in silicon. Of these, two of the most common are reactive ion etching in the gaseous phase and metal-assisted chemical etching (MACE) in the liquid phase. Though these two methods are highly established and characterized, there is a surprising scarcity of reports exploring the ability of metallic films to catalytically enhance the etching of silicon in dry plasmas via a MACE-like mechanism. Here, we discuss a <u>m</u>etal-<u>a</u>ssisted <u>p</u>lasma <u>e</u>tch (MAPE) performed using patterned gold films to catalyze the etching of silicon in an SF<sub>6</sub>/O<sub>2</sub> mixed plasma, selectively increasing the rate of etching by over 1000%. The degree of enhancement as a function of Au catalyst configuration and relative oxygen feed concentration is characterized, along with the catalytic activities of other common MACE metals including Ag, Pt, and Cu. Finally, methods of controlling the etch process are briefly explored to demonstrate the potential for use as a liquid-free fabrication strategy.

IN SITU ION BEAM ANALYSIS OF CHEMICAL AND PLASMA ETCHING OF Si

2001 ◽  
Vol 15 (28n29) ◽  
pp. 1419-1427
Author(s):  
KARUR R. PADMANABHAN
Keyword(s):  
Plasma Etching ◽  
Chemical Etching ◽  
Ion Beam ◽  
Etching Rate ◽  
Surface Damage ◽  
Moderate Increase ◽  
Ion Beam Analysis ◽  
Beam Analysis ◽  
Etched Surface

The possibility of carrying out in situ ion beam analysis of a gas-solid interface using RBS/Channeling techniques has been investigated using chemical and plasma etching of Si . A specially constructed thin Si window cell is used to initiate chemical etching of Si using Xe F 2. Analysis of etched Si surface using conventional, micro RBS/Channeling and computer simulated channeling spectra indicates a smooth damage free surface with fairly uniform etching. A moderate increase in etching rate and channeling χ min is observed in the presence of the analyzing beam. The results of chemical etching are compared with that due to Ar + and Xe + plasma induced etching of Si . In situ microbeam channeling analysis with CCM (Channeling Contrast Microscopy) of the plasma-etched surface indicates distinct differences in both etching rate and damage profile of Si (100) surface. The etching rate enhancement and damage profile have been explained using conventional TRIM analysis and ion beam surface damage.

Etching Properties of Hydrogenated Amorphous Silicon

1991 ◽  
Vol 219 ◽  
Author(s):  
Y. S. Tsuo ◽  
Y. Xu ◽  
D. W. Baker ◽  
S.K Deb
Keyword(s):  
Amorphous Silicon ◽  
Plasma Etching ◽  
Hydrogen Content ◽  
Chemical Etching ◽  
Isopropyl Alcohol ◽  
Hydrogen Plasma ◽  
Hydrogenated Amorphous Silicon ◽  
Wet Chemical ◽  
Wet Chemical Etching ◽  
Hydrogenated Amorphous

ABSTRACTWe have studied wet-chemical and dry etching properties of doped and undoped hydrogenated amorphous silicon (a-Si:H) films with bonded hydrogen content varying from 0 to 20 at.%. Etching processes studied include (1) wet-chemical etching using solutions of KOH, isopropyl alcohol (IPA), and H2O, (2) hydrogen plasma etching, and (3) XeF2 vapor etching.

Isothermal Stress Relaxation in Al, Alcu and A1vpd Films

1996 ◽  
Vol 436 ◽  
Author(s):  
J. P. Lokker ◽  
J. F. Jongste ◽  
G. C. A. M. Janssen ◽  
S. Radelaar
Keyword(s):  
Stress Relaxation ◽  
Integrated Circuits ◽  
Tensile Stress ◽  
Thermal Cycling ◽  
Mechanical Behavior ◽  
Mechanical Stress ◽  
Plasma Etching ◽  
Isothermal Treatment ◽  
Aluminum Metallization ◽  
Curvature Measurements

AbstractMechanical stress and its relaxation in aluminum metallization in integrated circuits (IC) are a major concern for the reliability of the material. It is known that adding Cu improves the reliability but complicates plasma etching and increases corrosion sensitivity. The mechanical behavior of AlVPd, AlCu and Al blanket films is investigated by wafer curvature measurements. During thermal cycling between 50°C and 400°C the highest tensile stress is found in AlVPd. In a subsequent experiment, the cooling was interrupted at several temperatures to investigate the stress behavior during an eight hour isothermal treatment. Isothermal stress relaxation has been observed in the three types of films and is discussed.

Use of ion milling to expose and highlight defects on cross-sectioned integrated circuits

1989 ◽  
Vol 47 ◽  
pp. 720-721
Author(s):  
K.H. Martinek ◽  
J.P. Benedict ◽  
S.J. Klepeis ◽  
T. Joseph ◽  
G. Vandygrift
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Chemical Etching ◽  
Initial Period ◽  
Sample Holder ◽  
Ion Milling ◽  
Block Method ◽  
Short Period ◽  
Circuit Defects ◽  
A Current

Polishing and cross-sectioning of integrated circuits is standard practice in failure analysis. With most integrated circuit defects, all that is usually needed is mechanical polishing to the cross-sectioned plane of interest. The sample is then ready for examination in the scanning electron microscope (SEM). However, some defects are too small or too subtle to be seen without delineating them in some way. Chemical etching is useful in many situations but sometimes does not highlight the defect and may introduce artifacts. In this experiment, cross-sectioned chips were ion milled for a short period to highlight or uncover defects.After locating failing transistors, samples were cross-sectioned on diamond paper using the open block method (i.e., not encapsulated in epoxy). A special ion mill sample holder was designed to accommodate the polishing fixture. This holder is inserted into the ion mill. (This eliminates the need to transfer the chip from one fixture to another, avoiding damage or contamination.) Samples were milled in a Gatan ion mill for an initial period of two minutes at a 20 degree tilt. A current of ˙5 mA and voltage of 5 kV were used. Samples were positioned so that maximum milling occurred in the area of the failing transistors.

Sign in / Sign up

Export Citation Format

Share Document