Packaging of MEMS for Integrated RF Circuit Verifications

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000926-000951
Author(s):  
Bruce C. Kim ◽  
Sai Evana ◽  
Rahim Kasim
Keyword(s):  
Low Voltage ◽  
Cell Phones ◽  
Deep Submicron ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Cmos Circuits ◽  
Test Technique ◽  
Mems Switches ◽  
Network Routers ◽  
Noise Amplifier

This paper provides development of MEMS switches and packaging of MEMS to test radio frequency circuits used in wireless products such as cell phones and network routers. We discuss fabrication of MEMS using low voltage magnetic materials and their configurations to achieve the optimum switch to test RF low noise amplifiers. We have accomplished a very unique methodology to test low noise amplifiers using built-in sellf-test technique and our MEMS switches are proposed to achieve the verification of low noise amplifiers. Furthermore, we have used MEMS switches that we developed to perform self calibration to correct for the parametric variations and faults within the deep submicron CMOS circuits. We also discuss packaging of MEMS and low noise amplifier using 3D TSV technology.

Modeling and Simulation of 3D MEMS Integrated RF Circuits

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 002006-002027
Author(s):  
Bruce Kim ◽  
Sukeshwar Kannan ◽  
Anurag Gupta ◽  
Naga Sai Evana
Keyword(s):  
Additive White Gaussian Noise ◽  
Rf Circuits ◽  
Low Noise ◽  
Waveform Generator ◽  
Test Technique ◽  
Mems Switches ◽  
Self Testing ◽  
3D Packaging ◽  
Noise Amplifier ◽  
Rf Circuit

Today's integrated packaging consists of analog, mixed-signal and RF circuits. These integrated packages are now available in 3-D which makes it extremely difficult to test for defects and their circuit functionalities. This paper provides 3D MEMS integrated packaging which provides self testing and calibrations to overcome process defects and out of spec circuits inside the package making the package self heal itself in case of faults and defects. We have worked on TSV based 3D packaging with MEMS switches to perform self calibrations. We developed a novel multi-tone dither test technique where the test stimulus is generated by modulating the RF carrier signal with a multi-tone signal generated on an Arbitrary Waveform Generator (AWG) with additive white Gaussian noise. We used arrays of MEMS switches to perform self testing. We have considered a low noise amplifier as the reference RF circuit which operates between 4 GHz and 6 GHz. The entire validation of the design using test technique and self-calibration of the RF circuit is automated using the calibration algorithm. The paper presents defects in TSV due to mechanical stress and thermal changes.

scholarly journals A 219-µW ultra-low power low-noise amplifier for IEEE 802.15.4 based battery powered, portable, wearable IoT applications

2021 ◽  
Vol 3 (4) ◽  
Author(s):  
S. Chrisben Gladson ◽  
Adith Hari Narayana ◽  
V. Thenmozhi ◽  
M. Bhaskar
Keyword(s):  
Low Power ◽  
Ieee 802.15.4 ◽  
Low Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Process Technology ◽  
Ultra Low Power ◽  
Power Mode ◽  
Noise Amplifier

AbstractDue to the increased processing data rates, which is required in applications such as fifth-generation (5G) wireless networks, the battery power will discharge rapidly. Hence, there is a need for the design of novel circuit topologies to cater the demand of ultra-low voltage and low power operation. In this paper, a low-noise amplifier (LNA) operating at ultra-low voltage is proposed to address the demands of battery-powered communication devices. The LNA dual shunt peaking and has two modes of operation. In low-power mode (Mode-I), the LNA achieves a high gain ($$S21$$ S 21 ) of 18.87 dB, minimum noise figure ($${NF}_{min.}$$ NF m i n . ) of 2.5 dB in the − 3 dB frequency range of 2.3–2.9 GHz, and third-order intercept point (IIP3) of − 7.9dBm when operating at 0.6 V supply. In high-power mode (Mode-II), the achieved gain, NF, and IIP3 are 21.36 dB, 2.3 dB, and 13.78dBm respectively when operating at 1 V supply. The proposed LNA is implemented in UMC 180 nm CMOS process technology with a core area of $$0.40{\mathrm{ mm}}^{2}$$ 0.40 mm 2 and the post-layout validation is performed using Cadence SpectreRF circuit simulator.

scholarly journals Low-voltage CMOS low-noise amplifier using planar-interleaved transformer

2001 ◽  
Vol 37 (8) ◽  
pp. 497 ◽  
Author(s):  
Chih-Chun Tang ◽  
Shen-Iuan Liu
Keyword(s):  
Low Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Noise Amplifier

Triple-Band CMOS Low Noise Amplifier Design Utilizing Transformer Couplings

2016 ◽  
Vol 698 ◽  
pp. 142-148
Author(s):  
Masataka Kamiyama ◽  
Daiki Oki ◽  
Satoru Kawauchi ◽  
Cong Bing Li ◽  
Nobuo Takahashi ◽  
...  
Keyword(s):  
Low Noise ◽  
Low Noise Amplifier ◽  
Dual Band ◽  
Low Noise Amplifiers ◽  
Coupling Coefficients ◽  
Input Matching ◽  
Simulation Results ◽  
Amplifier Design ◽  
Noise Amplifier ◽  
Triple Band

This paper describes multi-band low noise amplifiers (LNAs) utilizing input matching transformers. We investigate a conventional dual-band LNA circuit utilizing a transformer, and show our analysis and simulation results for its circuit. Based on this, we propose a triple band LNA with transformers. We have calculated characteristics of the dual-band and triple-band LNAs. As the results, the LNAs show gain of 20dB while maintaining good input matching, in the frequencies at 2.59GHz, 3.50GHz and 5.41 GHz. Then we discuss configuration and design of coupling coefficients of the transformers.

A fully integrated low voltage (0.5 V) X-band CMOS low noise amplifier

2010 ◽  
Vol 53 (1) ◽  
pp. 17-20 ◽  
Author(s):  
Baohong Liu ◽  
Jianjun Zhou ◽  
Junfa Mao
Keyword(s):  
Low Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Fully Integrated ◽  
X Band ◽  
Noise Amplifier
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