A Methodology for Chip - Package Interaction (CPI) Modeling in 3D IC Structures

Chip-Package Interaction (CPI) is a significant concern for modern electronic devices and this concern is magnified for 3D Stacked IC. Hard bumps, soft dielectrics, thin die and complex geometries of the stacked die require an ability to model and evaluate the interactions and risks. In packaged IC, dissimilar materials along with the thermal history during the assembly process results in significant residual stresses. These stresses can impact process yields, reliability and die electrical performance. Examples of these effects are ball cracking, ILD/ELK cracking or delamination and shifts in the behavior of sensitive devices such as transistors in analog circuits. Traditionally modeling and evaluation of these risks have been handled by different groups/companies (foundry, OSAT, Fabless Device Mfg) and have been hindered by the difficulty of using different tools and more importantly collaborating without revealing proprietary models and process information/recipes. In this paper we present a modeling flow which incorporates a seamless interface between the tools traditionally used for both package and silicon modeling. This is accomplished by utilizing Boundary Conditions (BC's) to act as a hand-off between the two simulation tools. A package level modeling approach is developed incorporating package assembly processes to predict residual stresses at the end of package assembly process. This package level simulator uses a nested sub-modeling approach for detailed extraction of stresses at different locations within BEOL layers of die, u-bumps, and C4 bumps from package level simulations. Additionally, it allows complete flexibility in selecting boundaries at chip-package interface and then the extraction of BC's necessary for die and transistor level simulations. These boundaries for Chip-Package Interaction are selected by the device manufacturer and the output from this simulation is fed into device level simulations. To provide flexibility for the user and to attain quick turnaround time, a web hosted interface is enabled to run package simulations online. The capabilities of this modeling approach are demonstrated by studying the impact of design and material parameters on stresses at various interconnect structures constituting a typical 3D IC stack package. An example of active silicon layer stress correlation from package level model and die-level model will be presented, thus validating this overall modeling flow.

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Modeling in the Cloud: Web Hosted CPI Modeling for Fabless Design Houses and OSATs Method for Mechanical Stress Simulation across the Chip & Package Domains in 3D IC's

International Symposium on Microelectronics ◽

10.4071/isom-2012-thp12 ◽

2012 ◽

Vol 2012 (1) ◽

pp. 001026-001033

Author(s):

Mark Nakamoto ◽

Karthikeyan Dhandapani ◽

Wei Zhao ◽

Ahmer Syed ◽

Wei Lin ◽

...

Keyword(s):

Residual Stresses ◽

Dissimilar Materials ◽

Turnaround Time ◽

Electrical Performance ◽

Assembly Process ◽

Package Design ◽

Simulation Tools ◽

Hand Off ◽

Device Manufacturer ◽

Soft Dielectrics

Chip-Package Interaction (CPI) is a significant concern for modern electronic devices and this concern is magnified for 3D Stacked IC. Hard bumps, soft dielectrics, thin die and complex geometries of the stacked die require ability to model and evaluate the interactions and risks. In packaged IC, dissimilar materials along with the thermal history during the assembly process results in significant residual stresses. These stresses can impact process yields, reliability and die electrical performance. Traditionally modeling and evaluation of these risks have been handled by different groups/companies (foundry, OSAT, Fabless Device Mfg) and have been hindered by the difficulty of using different tools and more importantly collaborating without revealing proprietary models and process information/recipes. In this paper we present a modeling flow which incorporates an interface between the tools traditionally used for both package and silicon modeling. This is accomplished by utilizing Boundary Conditions (BC's) to act as a hand-off between the two simulation tools. A package level modeling approach is developed incorporating package assembly processes to predict residual stresses at the end of package assembly process. It allows flexibility in selecting boundaries at chip-package interface and then the extraction of BC's necessary for die and transistor level simulations. These boundaries for Chip-Package Interaction are selected by the device manufacturer and the output from this simulation is fed into device level simulations. To provide flexibility for the user and to attain quick turnaround time, a web hosted interface is enabled to run package simulations online. Examples are presented to demonstrate the influence and impacts of materials, process recipes and chip/package design; including an example of the flow from package level through silicon electrical level modeling to silicon hardware measurements.

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Thermo-Mechanical Reliability of Through Silicon Vias (TSVs) and Solder Interconnects in 3-Dimensional Integrated Circuits

ASME 2009 InterPACK Conference, Volume 2 ◽

10.1115/interpack2009-89056 ◽

2009 ◽

Author(s):

Leila J. Ladani ◽

Omar Rodriguez

Keyword(s):

Solder Joints ◽

Silicon Layer ◽

Copper Interconnects ◽

Influential Factor ◽

Design Parameters ◽

Temperature Cycle ◽

Optimum Level ◽

3D Ic ◽

3 Dimensional ◽

The Impact

3-dimensional integrated circuit (3D IC) is a promising technology in today’s IC packaging industry. Since the technology is in infancy stages, many aspects of this technology are still under heavy investigation. Reliability of through silicon via (TSV) interconnects and interlayer bonding between the silicon layers are issues that become more complicated in 3D ICs due to complexity of the architecture and miniaturized interconnects. Optimizing design of these devices is essential in order to avoid short fatigue life of interconnects. This manuscript addresses the impact of design parameters such as die thickness, TSV diameter, TSV pitch, underfill thickness and underfill properties on thermo-mechanical durability of Direct Chip Attach (DCA) solder joints and TSV interconnects used in a 3D IC packages. A design was proposed where DCA is used to connect 4 layers of ICs and TSVs are used to connect the active layer of the dies to the second silicon layer. Solder joints, as small as 50-micron diameter, were used to attach silicon layers. A numerical experiment is designed to vary design parameters at 3 levels using L9 ortagonal array. A 3-dimensional model of the package was built and model was solved under an accelerated temperature cycle loading. Solder is considered as visco-plastic material and copper interconnects are assumed to follow bilinear isotropic hardening behavior. Two continuum damage models, energy partitioning and Coffin-Manson models, were used to assess the number of cycles to failure for solder joints and TSV copper interconnects respectively. Minitab software was used to analyze the result of experiment. The most influential factors on durability of solder interconnect are found to be underfill properties and height. However, the most influential factor on TSV durability is found to be TSV diameter. A non-linear response was observed for TSV pitch and diameter indicating that the optimum level may be in the range selected.

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The Impact of School Environment and Grade Level on Student Delinquency: A Multilevel Modeling Approach

10.21428/1163c5ca.bc7c5349 ◽

2020 ◽

Author(s):

Celia C. Lo ◽

Young S. Kim ◽

Thomas Allen ◽

Andrea Allen ◽

P. Allison Minugh ◽

...

Keyword(s):

Multilevel Modeling ◽

School Environment ◽

Grade Level ◽

Modeling Approach ◽

The Impact

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Electrical-Thermal-Reliability Co-Design for TSV-Based 3D-ICs

Volume 1: Thermal Management ◽

10.1115/ipack2015-48386 ◽

2015 ◽

Cited By ~ 3

Author(s):

Tiantao Lu ◽

Ankur Srivastava

Keyword(s):

Mechanical Stress ◽

Electrical Performance ◽

Mechanical Reliability ◽

Thermal Reliability ◽

Conduction Path ◽

Placement Problem ◽

Thermal Profile ◽

3D Ic ◽

3D Ics ◽

Simulation Based

This paper presents an electrical-thermal-reliability co-design technique for TSV-based 3D-ICs. Although TSV-based 3D-IC shows significant electrical performance improvement compared to traditional 2D circuit, researchers have reported strong electromigration (EM) in TSVs, which is induced by the thermal mechanical stress and the local temperature hotspot. We argue that rather than addressing 3D-IC’s EM issue after the IC designing phase, the designer should be aware of the circuit’s thermal and EM properties during the IC designing phase. For example, one should be aware that the TSVs establish vertical heat conduction path thus changing the chip’s thermal profile and also produce significant thermal mechanical stress to the nearby TSVs, which deteriorates other TSV’s EM reliability. Therefore, the number and location of TSVs play a crucial role in deciding 3D-IC’s electrical performance, changing its thermal profile, and affecting its EM-reliability. We investigate the TSV placement problem, in order to improve 3D-IC’s electrical performance and enhance its thermal-mechanical reliability. We derive and validate simple but accurate thermal and EM models for 3D-IC, which replace the current employed time-consuming finite-element-method (FEM) based simulation. Based on these models, we propose a systematic optimization flow to solve this TSV placement problem. Results show that compared to conventional performance-centered technique, our design methodology achieves 3.24x longer EM-lifetime, with only 1% performance degradation.

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Influence of Phase Transformations on Residual Stresses in Welded Structures

Volume 6B: Materials and Fabrication ◽

10.1115/pvp2013-97684 ◽

2013 ◽

Author(s):

R. J. Dennis ◽

R. Kulka ◽

O. Muransky ◽

M. C. Smith

Keyword(s):

Phase Transformation ◽

Residual Stresses ◽

Phase Transformations ◽

Numerical Models ◽

Material Model ◽

Transformation Model ◽

Austenitic Steels ◽

Beam Specimen ◽

Welded Structures ◽

The Impact

A key aspect of any numerical simulation to predict welding induced residual stresses is the development and application of an appropriate material model. Often significant effort is expended characterising the thermal, physical and hardening properties including complex phenomena such as high temperature annealing. Consideration of these aspects is sufficient to produce a realistic prediction for austenitic steels, however ferritic steels are susceptible to solid state phase transformations when heated to high temperatures. On cooling a reverse transformation occurs, with an associated volume change at the isothermal transformation temperature. Although numerical models exist (e.g. Leblond) to predict the evolution of the metallurgical phases, accounting for volumetric changes, it remains a matter of debate as to the magnitude of the impact of phase transformations on residual stresses. Often phase transformations are neglected entirely. In this work a simple phase transformation model is applied to a range of welded structures with the specific aim of assessing the impact, or otherwise, of phase transformations on the magnitude and distribution of predicted residual stresses. The welded structures considered account for a range of geometries from a simple ferritic beam specimen to a thick section multi-pass weld. The outcome of this work is an improved understanding of the role of phase transformation on residual stresses and an appreciation of the circumstances in which it should be considered.

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