Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration

2018 ◽  
Vol 15 (4) ◽  
pp. 141-147 ◽  
Author(s):  
Cheng-Ta Ko ◽  
Henry Yang ◽  
John Lau ◽  
Ming Li ◽  
Margie Li ◽  
...  
Keyword(s):  
Seed Layer ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Assembly Process ◽  
Molding Compound ◽  
Printed Circuit ◽  
Chip Size ◽  
Design Materials ◽  
Dry Film

Abstract The design, materials, process, and fabrication of a heterogeneous integration of four chips by a fan-out panel-level packaging (FOPLP) method are investigated in this study. Emphasis is placed on (1) the application of a dry-film epoxy molding compound for molding the chips and (2) the application of a special assembly process called uni-substrate-integrated package for fabricating the redistribution layers (RDLs) of the FOPLP. The Ajinomoto build-up film is used as the dielectric of the RDLs and is built up by the semiadditive process. Electroless Cu is used to make the seed layer, laser direct imaging is used for opening the photoresist, and printed circuit board (PCB) Cu plating is used for making the conductor wiring of the RDLs. The panel dimensions are 508 × 508 mm. The package dimensions of the FOPLP are 10 × 10 mm. The large chip size and the small chip sizes are, respectively, 5 × 5 mm and 3 × 3 mm. The uniqueness of this study is that all the processes are carried out by using the PCB equipment.

Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration

2018 ◽  
Vol 2018 (1) ◽  
pp. 000057-000063 ◽  
Author(s):  
Cheng-Ta Ko ◽  
Henry Yang ◽  
John Lau ◽  
Ming Li ◽  
Margie Li ◽  
...  
Keyword(s):  
Seed Layer ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Additive Process ◽  
Molding Compound ◽  
Printed Circuit ◽  
Chip Size ◽  
Design Materials ◽  
Dry Film

Abstract The design, materials, process, and fabrication of a heterogeneous integration of 4 chips by a FOPLP (fanout panel-level packaging) method are investigated in this study. Emphasis is placed on (a) the application of a dry-film EMC (epoxy molding compound) for molding the chips, and (b) the application of a special assembly process called Uni-SIP (uni-substrate-integrated-package) for fabricating the RDLs (redistribution layers) of the FOPLP. The ABF (Ajinomoto build-up film) is used as the dielectric of the RDLs and is built up by the SAP (semi-additive process). The electroless Cu is used to make the seed layer, the LDI (laser direct imaging) is used for opening the photoresist, and the PCB (printed circuit board) Cu plating is used for making the conductor wiring of the RDLs. The panel dimensions are 508mm × 508mm. The package dimensions of the FOPLP are 10mm × 10mm. The large chip size and the small chip sizes are, respectively 5mm × 5mm and 3mm × 3mm.

Reliability of Fan-Out Wafer-Level Heterogeneous Integration

2018 ◽  
Vol 15 (4) ◽  
pp. 148-162 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Yang Lei ◽  
Margie Li ◽  
Iris Xu ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Thermal Cycling Test ◽  
Wafer Level ◽  
Molding Compound ◽  
Shock Test ◽  
Cycling Test

Abstract In this study, the reliability (thermal cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5 × 5 mm), three small chips (3 ×3 mm), and four capacitors (0402) embedded in an epoxy molding compound package (10 × 10 mm) with two redistribution layers (RDLs) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a six-layer PCB. The sample sizes for the thermal cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.

The applicability of electrodeposited photoresists in producing ultra‐fine lines using sputtered seeding layers

Circuit World ◽  
2002 ◽  
Vol 28 (2) ◽  
pp. 11-13 ◽  
Author(s):  
Paavo Jalonen ◽  
Aulis Tuominen
Keyword(s):  
Printed Circuit Board ◽  
Circuit Board ◽  
Core Material ◽  
Quality Properties ◽  
Printed Circuit ◽  
Printed Circuit Board Manufacturing ◽  
Coating Method ◽  
Film Method ◽  
Seed Layers ◽  
Dry Film

Photolithographic techniques are universally employed in multi‐layer printed circuit board manufacturing. The growing demand for miniaturization of electronics means that finer lines and smaller vias are increasingly required and these very fine lines on the substrate are increasingly difficult to produce by conventional means. One very promising means of meeting these fine line requirements is via the etching of sputtered thin films on a substrate and then growing copper on these lines using an additive method. In this work we tested the capability of an electrodeposited, positive‐acting photoresist for patterning thin film circuits on sputtered seed layers such as chromium. A fully additive electroless copper was then used to produce the copper lines. Epoxy reinforced fibreglass was used as a core material. The performance and quality properties of the process were examined, along with limitations of the process when compared with both a conventional dry film method and a spin coating method.

Reliability of Fan-Out Wafer-Level Heterogeneous Integration

2018 ◽  
Vol 2018 (1) ◽  
pp. 000224-000232 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Yang Lei ◽  
Margie Li ◽  
Iris Xu ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Thermal Cycling Test ◽  
Wafer Level ◽  
Molding Compound ◽  
Shock Test ◽  
Cycling Test

Abstract In this study, the reliability (thermal-cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5mm×5mm), three small chips (3mm×3mm), and 4 capacitors (0402) embedded in an epoxy molding compound (EMC) package (10mm×10mm) with two RDLs (redistribution layers) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging (FOWLP) is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a 6-layer PCB. The sample sizes for the thermal-cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal-cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal-cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.

scholarly journals Chip-Last (RDL-First) Fan-Out Panel-Level Packaging (FOPLP) for Heterogeneous Integration

2020 ◽  
Vol 17 (3) ◽  
pp. 89-98
Author(s):  
John H. Lau ◽  
Cheng-Ta Ko ◽  
Chia-Yu Peng ◽  
Kai-Ming Yang ◽  
Tim Xia ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Printed Circuit Board ◽  
Drop Test ◽  
Circuit Board ◽  
Reliability Test ◽  
Heterogeneous Integration ◽  
Test Results ◽  
Glass Panel ◽  
Printed Circuit

Abstract In this investigation, the chip-last, redistribution-layer (RDL)–first, fan-out panel-level packaging (FOPLP) for heterogeneous integration is studied. Emphasis is placed on the materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10 × 10 mm2) and two small chips (7 × 5 mm2) by an FOPLP method on a 20 × 20-mm2 RDL-first substrate fabricated on a 515 × 510 mm2 temporary glass panel. Reliability test such as the drop test of the heterogeneous integration package on a printed circuit board (PCB) is performed, and test results including failure analysis are presented. Some recommendations are also provided.

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