scholarly journals Chip-Last (RDL-First) Fan-Out Panel-Level Packaging (FOPLP) for Heterogeneous Integration

2020 ◽  
Vol 17 (3) ◽  
pp. 89-98
Author(s):  
John H. Lau ◽  
Cheng-Ta Ko ◽  
Chia-Yu Peng ◽  
Kai-Ming Yang ◽  
Tim Xia ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Printed Circuit Board ◽  
Drop Test ◽  
Circuit Board ◽  
Reliability Test ◽  
Heterogeneous Integration ◽  
Test Results ◽  
Glass Panel ◽  
Printed Circuit

Abstract In this investigation, the chip-last, redistribution-layer (RDL)–first, fan-out panel-level packaging (FOPLP) for heterogeneous integration is studied. Emphasis is placed on the materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10 × 10 mm2) and two small chips (7 × 5 mm2) by an FOPLP method on a 20 × 20-mm2 RDL-first substrate fabricated on a 515 × 510 mm2 temporary glass panel. Reliability test such as the drop test of the heterogeneous integration package on a printed circuit board (PCB) is performed, and test results including failure analysis are presented. Some recommendations are also provided.

Chip-Last (RDL-First) Fan-Out Panel-Level Packaging (FOPLP) for Heterogeneous Integration

2020 ◽  
Vol 2020 (1) ◽  
pp. 000042-000050
Author(s):  
John H Lau ◽  
Cheng-Ta Ko ◽  
Chia-Yu Peng ◽  
Kai-Ming Yang ◽  
Tim Xia ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Printed Circuit Board ◽  
Drop Test ◽  
Circuit Board ◽  
Reliability Test ◽  
Heterogeneous Integration ◽  
Test Results ◽  
Glass Panel ◽  
Printed Circuit

Abstract In this investigation, the chip-last, RDL (redistribution-layer)-first, fan-out panel-level packaging (FOPLP) for heterogeneous integration is studied. Emphasis is placed on the materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10mm × 10mm) and two small chips (7mm × 5mm) by a FOPLP method on a 20mm × 20mm RDL-first substrate fabricated on a 515mm × 510mm temporary glass panel. Reliability test such as the drop test of the heterogeneous integration package on a PCB (printed circuit board) is performed and test results including failure analysis are presented. Some recommendations are also provided.

Numerical Simulation and Experimental Measurement of a Printed Circuit Board Subjected to Drop Test

2009 ◽  
Vol 419-420 ◽  
pp. 37-40
Author(s):  
Shiuh Chuan Her ◽  
Shien Chin Lan ◽  
Chun Yen Liu ◽  
Bo Ren Yao
Keyword(s):  
Finite Element ◽  
Experimental Measurement ◽  
Test Specimen ◽  
Printed Circuit Board ◽  
Drop Impact ◽  
Simulation Technique ◽  
Drop Test ◽  
Circuit Board ◽  
Printed Circuit ◽  
The Impact

Drop test is one of the common methods for determining the reliability of electronic products under actual transportation conditions. The aim of this study is to develop a reliable drop impact simulation technique. The test specimen of a printed circuit board is clamped at two edges on a test fixture and mounted on the drop test machine platform. The drop table is raised at the height of 50mm and dropped with free fall to impinge four half-spheres of Teflon. One accelerometer is mounted on the center of the specimen to measure the impact pulse. The commercial finite element software ANSYS/LS-DYNA is applied to compute the impact acceleration and dynamic strain on the test specimen during the drop impact. The finite element results are compared to the experimental measurement of acceleration with good correlation between simulation and drop testing. With the accurate simulation technique, one is capable of predicting the impact response and characterizing the failure mode prior to real reliability test.

Numerical Model to Simulate the Drop Test of Printed Circuit Board (PCB)

2011 ◽  
Vol 423 ◽  
pp. 26-30
Author(s):  
S. Assif ◽  
M. Agouzoul ◽  
A. El Hami ◽  
O. Bendaou ◽  
Y. Gbati
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Drop Test ◽  
Dynamic Responses ◽  
Circuit Board ◽  
Joint Stress ◽  
Printed Circuit ◽  
Increasing Demand ◽  
Improved Model ◽  
Board Level

Increasing demand for smaller consumer electronic devices with multi-function capabilities has driven the packaging architectures trends for the finer-pitch interconnects, thus increasing chances of their failures. A simulation of the Board Level Drop-Test according to JEDEC (Joint Electron Device Council) is performed to evaluate the solder joint reliability under drop impact test. After good insights to the physics of the problem, the results of the numerical analysis on a simple Euler-Bernoulli beam were validated against analytical analysis. Since the simulation has to be performed on ANSYS Mechanical which is an implicit software, two methods were proposed, the acceleration-input and the displacement-input. The results are the same for both methods. Therefore, the simulation is carried on the real standard model construction of the board package level2. Then a new improved model is proposed to satisfy shape regular element and accuracy. All the models are validated to show excellent first level correlation on the dynamic responses of Printed Circuit Board, and second level correlation on solder joint stress. Then a static model useful for quick design analysis and optimization’s works is proposed and validated. Finally, plasticity behavior is introduced on the solder ball and a non-linear analysis is performed.

Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration

2018 ◽  
Vol 15 (4) ◽  
pp. 141-147 ◽  
Author(s):  
Cheng-Ta Ko ◽  
Henry Yang ◽  
John Lau ◽  
Ming Li ◽  
Margie Li ◽  
...  
Keyword(s):  
Seed Layer ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Assembly Process ◽  
Molding Compound ◽  
Printed Circuit ◽  
Chip Size ◽  
Design Materials ◽  
Dry Film

Abstract The design, materials, process, and fabrication of a heterogeneous integration of four chips by a fan-out panel-level packaging (FOPLP) method are investigated in this study. Emphasis is placed on (1) the application of a dry-film epoxy molding compound for molding the chips and (2) the application of a special assembly process called uni-substrate-integrated package for fabricating the redistribution layers (RDLs) of the FOPLP. The Ajinomoto build-up film is used as the dielectric of the RDLs and is built up by the semiadditive process. Electroless Cu is used to make the seed layer, laser direct imaging is used for opening the photoresist, and printed circuit board (PCB) Cu plating is used for making the conductor wiring of the RDLs. The panel dimensions are 508 × 508 mm. The package dimensions of the FOPLP are 10 × 10 mm. The large chip size and the small chip sizes are, respectively, 5 × 5 mm and 3 × 3 mm. The uniqueness of this study is that all the processes are carried out by using the PCB equipment.

Failure Analysis of Halogen-Free Printed Circuit Board Assembly Under Board-Level Drop Test

2012 ◽  
Vol 134 (1) ◽  
Author(s):  
Hung-Jen Chang ◽  
Chau-Jie Zhan ◽  
Tao-Chih Chang ◽  
Jung-Hua Chou
Keyword(s):  
Printed Circuit Board ◽  
Drop Test ◽  
Circuit Board ◽  
Printed Circuit Board Assembly ◽  
Printed Circuit ◽  
Plastic Ball ◽  
Circuit Board Assembly ◽  
Halogen Free ◽  
Board Level ◽  
The Impact

In this study, a lead-free dummy plastic ball grid array component with daisy-chains and Sn4.0Ag0.5Cu Pb-free solder balls was assembled on an halogen-free high density interconnection printed circuit board (PCB) by using Sn1.0Ag0.5Cu solder paste on the Cu pad surfaces of either organic solderable preservative (OSP) or electroless nickel immersion gold (ENIG). The assembly was tested for the effect of the formation extent of Ag3Sn intermetallic compound. Afterward a board-level pulse-controlled drop test was conducted on the as-reflowed assemblies according to the JESD22-B110 and JESD22-B111 standards, the impact performance of various surface finished halogen-free printed circuit board assembly was evaluated. The test results showed that most of the fractures occurred around the pad on the test board first. Then cracks propagated across the outer build-up layer. Finally, the inner copper trace was fractured due to the propagated cracks, resulting in the failure of the PCB side. Interfacial stresses numerically obtained by the transient stress responses supported the test observation as the simulated initial crack position was the same as that observed.

scholarly journals Research on the calibrated method for MEMS magnetometer arrays

2020 ◽  
Author(s):  
Zetao Guo ◽  
Xiang Xu ◽  
Tao zhang
Keyword(s):  
Printed Circuit Board ◽  
Experimental Tests ◽  
Measurement Model ◽  
General Purpose ◽  
Circuit Board ◽  
Test Results ◽  
Adaptive Kalman Filter ◽  
Unknown Parameters ◽  
Printed Circuit ◽  
Magnetometer Arrays

The MEMS magnetometer determines the orientation for the MEMS inertial system. Because of the large noise of the MEMS magnetometer and the interference of soft and hard iron outside, the measurement error of the MEMS magnetometer is large. To reduce the effects of the random noises, the MEMS magnetometer arrays are designed in this paper. In our design, thirty-two MEMS magnetometers are welding on a printed circuit board (PCB), which area is 5×5 cm2. The forty general-purpose input-output (GPIO) ports, which are thirty-two data ports and eight clock ports, are used to collect the data of MEMS magnetometers. Then, averaging the thirty-two measurements of the MEMS magnetometers, the random noises of the measurements of the MEMS magnetometers can be reduced. Based on the averaging operation for the collected sensors’ data, a unified measurement model for the MEMS magnetometer arrays is constructed. Using the unified measurement model, an adaptive Kalman filter is developed to estimate the unknown parameters. To validate the performance of the MEMS magnetometer arrays, the simulation and experimental tests are designed. The test results show that, comparing with the single MEMS magnetometer, the random noises of the MEMS magnetometer arrays are reduced effectively.

Failure analysis on cracking of blind and buried vias of printed circuit board for high-end mobile phones

2019 ◽  
Vol 31 (4) ◽  
pp. 203-210
Author(s):  
Jie Tang ◽  
Yi Gong ◽  
Zhen-Guo Yang
Keyword(s):  
Failure Analysis ◽  
Mobile Phones ◽  
Printed Circuit Board ◽  
Failure Mechanisms ◽  
Performance Testing ◽  
Circuit Board ◽  
Chemical Compositions ◽  
Content Type ◽  
Printed Circuit ◽  
Prevention Methods

Purpose The submitted paper is mainly concerned with the cracking of blind and buried vias of printed circuit board (PCB) for smartphones which were encountered with abnormal display problems like scramble display or no display during service and had to be recalled. Design/methodology/approach To found out the root causes of this failure and dissolve this commercial dispute, comprehensive failure analysis was performed on the printed circuit board assemblies (PCBAs) and PCBs of the failed smartphone, such as macrograph and micrograph observation, chemical compositions analysis, thermal performance testing and blind via pull-off experiment, which finally helped to determine the causes. Besides that, the failure mechanisms were discussed in detail, and pertinent countermeasures were proposed point by point. Findings It was found that the PCB blind vias cracking was the main reason for the scramble display or no display of the smartphone, and the incomplete cleaning process before copper plating was the root cause of the blind vias cracking. Practical implications Achievement of this paper would not only help to provide the solid evidence for determining the responsibility of this commercial dispute but also lead to a better understanding of the failure mechanisms and prevention methods for similar failure cases of other advanced mobile phones. Originality/value Most failure analysis researches of PCBAs only focused on the unqualified products from manufacturing, while this paper addressed a failure analysis case of PCBAs products for smartphones from actual services, which was relatively rarely reported in the past.

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