Formation of fine pitch solder bumps on polytetrafluoroethylene printed circuit board using dry film photoresist

The desire of students of SMK Muhammadiyah 2 Salam Magelang to be able to make a printed circuit board is something that is very important to be welcomed and followed up wisely so that the desire of the students is not just a wishful dream but will be a reality. This activity is meant to be an effort not only to overcome difficulties at certain times (short-term activities), but is expected to be sustainable for the future (longer term). Looking at the fact, of course, should be strived to realize the handling of the problem at least for the near term. For that required activities that are practical and immediate benefits can be taken as the activity can be a short course or short training. To solve the problem, it is realized by holding a short course / training course on PCB Layout Creation with DIP TRACE and Dry Film Photoresist technology followed by etching process, drilling and installation of components that will be useful for students who want to do the main final work related with the manufacture of tools / hardware. Keywords: Making PCB, DIP TRACE, Dry Photoresist film

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Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration

Journal of Microelectronics and Electronic Packaging ◽

10.4071/imaps.734552 ◽

2018 ◽

Vol 15 (4) ◽

pp. 141-147 ◽

Cited By ~ 10

Author(s):

Cheng-Ta Ko ◽

Henry Yang ◽

John Lau ◽

Ming Li ◽

Margie Li ◽

...

Keyword(s):

Seed Layer ◽

Printed Circuit Board ◽

Circuit Board ◽

Heterogeneous Integration ◽

Assembly Process ◽

Molding Compound ◽

Printed Circuit ◽

Chip Size ◽

Design Materials ◽

Dry Film

Abstract The design, materials, process, and fabrication of a heterogeneous integration of four chips by a fan-out panel-level packaging (FOPLP) method are investigated in this study. Emphasis is placed on (1) the application of a dry-film epoxy molding compound for molding the chips and (2) the application of a special assembly process called uni-substrate-integrated package for fabricating the redistribution layers (RDLs) of the FOPLP. The Ajinomoto build-up film is used as the dielectric of the RDLs and is built up by the semiadditive process. Electroless Cu is used to make the seed layer, laser direct imaging is used for opening the photoresist, and printed circuit board (PCB) Cu plating is used for making the conductor wiring of the RDLs. The panel dimensions are 508 × 508 mm. The package dimensions of the FOPLP are 10 × 10 mm. The large chip size and the small chip sizes are, respectively, 5 × 5 mm and 3 × 3 mm. The uniqueness of this study is that all the processes are carried out by using the PCB equipment.

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The applicability of electrodeposited photoresists in producing ultra‐fine lines using sputtered seeding layers

Circuit World ◽

10.1108/03056120210412805 ◽

2002 ◽

Vol 28 (2) ◽

pp. 11-13 ◽

Cited By ~ 3

Author(s):

Paavo Jalonen ◽

Aulis Tuominen

Keyword(s):

Printed Circuit Board ◽

Circuit Board ◽

Core Material ◽

Quality Properties ◽

Printed Circuit ◽

Printed Circuit Board Manufacturing ◽

Coating Method ◽

Film Method ◽

Seed Layers ◽

Dry Film

Photolithographic techniques are universally employed in multi‐layer printed circuit board manufacturing. The growing demand for miniaturization of electronics means that finer lines and smaller vias are increasingly required and these very fine lines on the substrate are increasingly difficult to produce by conventional means. One very promising means of meeting these fine line requirements is via the etching of sputtered thin films on a substrate and then growing copper on these lines using an additive method. In this work we tested the capability of an electrodeposited, positive‐acting photoresist for patterning thin film circuits on sputtered seed layers such as chromium. A fully additive electroless copper was then used to produce the copper lines. Epoxy reinforced fibreglass was used as a core material. The performance and quality properties of the process were examined, along with limitations of the process when compared with both a conventional dry film method and a spin coating method.

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Packaging Challenges of Thin High Bandwidth POP

Volume 10: Micro- and Nano-Systems Engineering and Packaging ◽

10.1115/imece2019-11181 ◽

2019 ◽

Author(s):

Fletcher (Cheng-Piao) Tung ◽

Jensen (Ying-Chou) Tsai ◽

Yu-Po Wang ◽

Joe (Chih-Nan) Lin ◽

Gary (Yue-Long) Fan

Keyword(s):

Printed Circuit Board ◽

Lower Cost ◽

Coefficient Of Thermal Expansion ◽

Cellular Phone ◽

Circuit Board ◽

Printed Circuit ◽

Fine Pitch ◽

High Bandwidth ◽

Application Processor ◽

Different Thickness

Abstract Components for Smartphone has been the biggest driving force of IC industry for years, and one of the most important IC is application processor (AP). AP needs to work with low power double data rate (LPDDR), the mobile DRAM together for the primary processing of cellular phone and other smart functions. At the beginning, they were packaged separately and then mounted onto printed circuit board (PCB) very close to each other. Nowadays, AP for flagship Smartphone is packaged with a variety of PoP (package on package) structures to shorten the communication distance between AP and LPDDR as well as to save more rooms for battery. High bandwidth package on package (HBW-POP) is the most popular structure among them. As compared to other substrate based PoP, HBW-POP provides the most top side pin count while keeps larger ball pitch for system assembly house to mount LPDDR packaged by fine-pitch ball grid array (FBGA) on top of it. And compared to novel Fan-Out based PoP, HBW-POP has lower cost for AP packaging. In addition, maximum package height of HBW-POP has been shrinking. It is because when LPDDR is mounted onto HBW-POP, the combination is always the tallest chips on the PCB, which determines how slim specific Smartphone can be. HBW-POP consists of 3 parts to encapsulate AP die, and they are top 2-layer substrate, middle molding and bottom 3-layer substrate. Each part has its own coefficient of thermal expansion (CTE) and rigidity, and the warpage performance of HBW-POP is important to align the warpage behavior of LPDDR. The warpage of HBW-POP needs to align with FBGA properly during reflow for good joint, but when HBW-POP becomes thinner, the rigidity of its different parts is changed, which result in different warpage behavior during the reflow. In this paper, we will review the challenges of thin HBW-POP packaging, meanwhile we will explore possible solutions to address each challenge. The study includes the screening of different thickness combination of the 3 parts of HBW-POP, and the optimization of the rigidity and CTE of them. Design of Experiments (DOE) are conducted to find solutions which can meet warpage target, and finally, we present more different tests to prove the reliability of our results.

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Shock and Vibration of Solder Bumped Flip Chip on Organic Coated Copper Boards

Journal of Electronic Packaging ◽

10.1115/1.2792127 ◽

1996 ◽

Vol 118 (2) ◽

pp. 101-104 ◽

Cited By ~ 27

Author(s):

John Lau ◽

Eric Schneider ◽

Tom Baker

Keyword(s):

Mathematical Analysis ◽

Flip Chip ◽

Printed Circuit Board ◽

Circuit Board ◽

Plane Shock ◽

Printed Circuit ◽

Flip Chips ◽

Solder Bumps ◽

Out Of Plane ◽

Vibration Tests

The reliability of solder bumped flip chips on organic coated copper (OCC) printed circuit board (PCB) has been studied by shock and vibration tests and a mathematical analysis. Two different chip sizes (7 mm and 14 mm on a side) have been studied, and the larger chips have many internal solder bumps. For the in-plane and out-of-plane and out-of-plane shock tests, the chips were assembled with and without underfill encapsulants. However, for the out-of-plane vibration tests all the chips were underfilled with epoxy.

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Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration

International Symposium on Microelectronics ◽

10.4071/2380-4505-2018.1.000057 ◽

2018 ◽

Vol 2018 (1) ◽

pp. 000057-000063 ◽

Cited By ~ 1

Author(s):

Cheng-Ta Ko ◽

Henry Yang ◽

John Lau ◽

Ming Li ◽

Margie Li ◽

...

Keyword(s):

Seed Layer ◽

Printed Circuit Board ◽

Circuit Board ◽

Heterogeneous Integration ◽

Additive Process ◽

Molding Compound ◽

Printed Circuit ◽

Chip Size ◽

Design Materials ◽

Dry Film

Abstract The design, materials, process, and fabrication of a heterogeneous integration of 4 chips by a FOPLP (fanout panel-level packaging) method are investigated in this study. Emphasis is placed on (a) the application of a dry-film EMC (epoxy molding compound) for molding the chips, and (b) the application of a special assembly process called Uni-SIP (uni-substrate-integrated-package) for fabricating the RDLs (redistribution layers) of the FOPLP. The ABF (Ajinomoto build-up film) is used as the dielectric of the RDLs and is built up by the SAP (semi-additive process). The electroless Cu is used to make the seed layer, the LDI (laser direct imaging) is used for opening the photoresist, and the PCB (printed circuit board) Cu plating is used for making the conductor wiring of the RDLs. The panel dimensions are 508mm × 508mm. The package dimensions of the FOPLP are 10mm × 10mm. The large chip size and the small chip sizes are, respectively 5mm × 5mm and 3mm × 3mm.

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Rapid Prototyping Tape Stencils for the Application of Solder Paste

International Symposium on Microelectronics ◽

10.4071/isom-2017-poster2_040 ◽

2017 ◽

Vol 2017 (1) ◽

pp. 000652-000658

Author(s):

Mimi X. Yang ◽

Karen Dowling ◽

Debbie Senesky ◽

H.-S. Philip Wong

Keyword(s):

Rapid Prototyping ◽

Printed Circuit Board ◽

Circuit Board ◽

Solder Paste ◽

Electrically Conductive ◽

Printed Circuit ◽

Solder Bumps ◽

Small Device ◽

Bond Pads ◽

Silicon Device

Abstract This works describes a promising method for rapid prototyping tape stencils for the application of solder paste. This process is appropriate for research settings requiring developmental flexibility and the ability to deal with small device dies. This work compares the volume of solder paste deposited versus aperture volume for several common tape materials and several common printed circuit board (PCB) stencil materials. The solder deposits are then reflowed to identify which aperture and solder paste parameters can generate successful solder bumps. Electrically conductive solder bonds for small bond pads (100 μm and larger) are demonstrated between silicon device dies and glass dies using this process.

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