Design challenges in Interposer based 3-D Memory Logic Interface

Further improvements in system performance are often limited by the achievable bandwidth between processor and memory. In this paper we look at interposer-based and stacked solutions to integrate processor and 3D memory into a high performance system. The comparison is made for different technological decisions, design problems faced for choosing a certain 3D memory type from Wide IO/1–2, High bandwidth memory (HBM) and Hybrid Memory Cube (HMC). Logic die size, metal layers and material of interposer affected by routing requirements of memory systems are discussed.

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High-throughput Near-Memory Processing on CNNs with 3D HBM-like Memory

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/3460971 ◽

2021 ◽

Vol 26 (6) ◽

pp. 1-20

Author(s):

Naebeom Park ◽

Sungju Ryu ◽

Jaeha Kung ◽

Jae-Joon Kim

Keyword(s):

Energy Consumption ◽

High Performance ◽

Three Dimensional ◽

Cmos Technology ◽

Memory Processing ◽

Hybrid Memory ◽

High Bandwidth ◽

Dataflow Models ◽

Accelerator Design ◽

3D Memory

This article discusses the high-performance near-memory neural network (NN) accelerator architecture utilizing the logic die in three-dimensional (3D) High Bandwidth Memory– (HBM) like memory. As most of the previously reported 3D memory-based near-memory NN accelerator designs used the Hybrid Memory Cube (HMC) memory, we first focus on identifying the key differences between HBM and HMC in terms of near-memory NN accelerator design. One of the major differences between the two 3D memories is that HBM has the centralized through- silicon-via (TSV) channels while HMC has distributed TSV channels for separate vaults. Based on the observation, we introduce the Round-Robin Data Fetching and Groupwise Broadcast schemes to exploit the centralized TSV channels for improvement of the data feeding rate for the processing elements. Using synthesized designs in a 28-nm CMOS technology, performance and energy consumption of the proposed architectures with various dataflow models are evaluated. Experimental results show that the proposed schemes reduce the runtime by 16.4–39.3% on average and the energy consumption by 2.1–5.1% on average compared to conventional data fetching schemes.

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Autonomous Microgrid Design Using Classifier-Guided Sampling

Volume 2A: 41st Design Automation Conference ◽

10.1115/detc2015-46107 ◽

2015 ◽

Author(s):

Peter B. Backlund ◽

John P. Eddy

Keyword(s):

High Performance ◽

Discrete Event ◽

Hurricane Sandy ◽

System Level ◽

Design Problems ◽

Event Simulation ◽

Performance System ◽

Performance Statistics ◽

The City ◽

Microgrid Design

Identifying high-performance, system-level microgrid designs is a significant challenge due to the overwhelming array of possible configurations. Uncertainty relating to loads, utility outages, renewable generation, and fossil generator reliability further complicates this design problem. In this paper, the performance of a candidate microgrid design is assessed by running a discrete event simulation that includes extended, unplanned utility outages during which microgrid performance statistics are computed. Uncertainty is addressed by simulating long operating times and computing average performance over many stochastic outage scenarios. Classifier-guided sampling, a Bayesian classifier-based optimization algorithm for computationally expensive design problems, is used to search and identify configurations that result in reduced average load not served while not exceeding a predetermined microgrid construction cost. The city of Hoboken, NJ, which sustained a severe outage following Hurricane Sandy in October, 2012, is used as an example of a location in which a well-designed microgrid could be of great benefit during an extended, unplanned utility outage. The optimization results illuminate design trends and provide insights into the traits of high-performance configurations.

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