SIMULATION AND ANALYSIS OF 3T AND 4T CNTFET DRAM DESIGN IN 32nm TECHNOLOGY

International Journal of Electronics Signals and Systems ◽

10.47893/ijess.2014.1197 ◽

2014 ◽

pp. 53-59

Author(s):

N. SOMORJIT SINGH ◽

DR.M. MADHESWARAN

Keyword(s):

Carbon Nanotube ◽

Power Dissipation ◽

Delay Time ◽

Field Effect ◽

Field Effect Transistors ◽

Leakage Power ◽

Memory Cells ◽

Time Dynamic

Carbon Nanotube Field Effect Transistors (CNTFETs) is a promising device alternative for future nanometersscale technology. This paper presents 3TCNTFET & 4TCNTFET simulation and analysis of DRAM with metallic CNTFET using a CNTFET SPICE(HSPICE) model with 32ns technology have shown the DRAM cells in terms of leakage power, power dissipation, delay time, dynamic write and read power. Here, comparison between 4TDRAM and 3TDRAM memory cells is also shown which 3TDRAM has better performance in power dissipation and leakage power than 4TDRAM cell, but less delay in 4TDRAM.

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CNTFET Circuit-Based Wide Fan-In Domino Logic for Low Power Applications

Journal of Circuits System and Computers ◽

10.1142/s0218126622500360 ◽

2021 ◽

pp. 2250036

Author(s):

Vijay Kumar Sharma

Keyword(s):

Power Dissipation ◽

Field Effect ◽

Performance Metrics ◽

Field Effect Transistors ◽

High Current Density ◽

Cylindrical Tube ◽

Leakage Power ◽

Oxide Semiconductor ◽

Domino Logic ◽

Leakage Power Dissipation

Carbon nanotube field effect transistors (CNTFETs) are the best alternative option for the metal oxide semiconductor field effect transistor (MOSFET) in the ultra-deep submicron (ultra-DSM) regime. CNTFET has numerous benefits such as lower off-state current, high current density, low bias potential and better transport property as compared to MOSFET. A rolled graphene sheet-based cylindrical tube is constructed in the channel region of the CNTFET structure. In this paper, an improved domino logic (IDL) configuration is proposed for domino logic circuits to improve the different performance metrics. An extensive comparative simulation analysis is provided for the different performance metrics for different circuits to verify the novelty of the proposed IDL approach. The IDL approach saves the leakage power dissipation by 95.61% and enhances the speed by 87.10% for the 4-bit full adder circuit as compared to the best reported available domino method. The effects of the number of carbon nanotubes (CNTs), temperature, and power supply voltage variations are estimated for leakage power dissipation for the 16-input OR (OR16) gate. The reliability of different performance metrics for different circuit is calculated in terms of uncertainty by running the Monte Carlo simulations for 500 samples. Stanford University’s 32[Formula: see text]nm CNTFET model is applied for circuit simulations.

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High-Efficient Circuits for Ternary Addition

VLSI Design ◽

10.1155/2014/534587 ◽

2014 ◽

Vol 2014 ◽

pp. 1-15 ◽

Cited By ~ 11

Author(s):

Reza Faghih Mirzaee ◽

Keivan Navi ◽

Nader Bagherzadeh

Keyword(s):

Carbon Nanotube ◽

Power Dissipation ◽

Field Effect ◽

Field Effect Transistors ◽

The Novel ◽

Ternary Addition ◽

Practical Applications ◽

High Efficient ◽

Static Power ◽

The One

New ternary adders, which are fundamental components of ternary addition, are presented in this paper. They are on the basis of a logic style which mostly generates binary signals. Therefore, static power dissipation reaches its minimum extent. Extensive different analyses are carried out to examine how efficient the new designs are. For instance, the ternary ripple adder constructed by the proposed ternary half and full adders consumes 2.33 μW less power than the one implemented by the previous adder cells. It is almost twice faster as well. Due to their unique superior characteristics for ternary circuitry, carbon nanotube field-effect transistors are used to form the novel circuits, which are entirely suitable for practical applications.

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