Static Power Reduction in 32-bit Ripple Carry Adder using Dual Threshold Voltage Assignment

Along with the fast development of dual-threshold voltage (dual-Vt) and multi-threshold technology, it is possible to use them to reduce static power in low-voltage high-performance circuits. In this paper, we propose a new method to realize CMOS digital circuits that are implemented with dual-Vt technology. We first present a new signal-path-level circuit model which effectively deals with the fact that there can be two threshold voltages assigned to a single gate. In order to assign proper threshold voltage to all the signal-paths in the circuit, our new algorithms introduce the concept of subcircuit extraction and include the hierarchy algorithms which are effective and fast. Experimental results show that our algorithms produce a significant reduction for the ISCAS85 benchmark circuits.

Download Full-text

NBTI-aware dual threshold voltage assignment for leakage power reduction

2012 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2012.6272033 ◽

2012 ◽

Cited By ~ 3

Author(s):

Wen-Pin Tu ◽

Shih-Wei Wu ◽

Shih-Hsu Huang ◽

Mely Chen Chi

Keyword(s):

Threshold Voltage ◽

Power Reduction ◽

Leakage Power ◽

Dual Threshold Voltage

Download Full-text

Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) ◽

10.1109/iscas.2013.6572291 ◽

2013 ◽

Cited By ~ 2

Author(s):

Jian Zhang ◽

Pierre-Emmanuel Gaillardon ◽

Giovanni De Micheli

Keyword(s):

Threshold Voltage ◽

Silicon Nanowire ◽

Dual Threshold Voltage ◽

Independent Gate

Download Full-text

An Efficient Power Optimized 32 bit BCD Adder Using Multi-Channel Technique

International Journal of New Practices in Management and Engineering ◽

10.17762/ijnpme.v6i02.57 ◽

2017 ◽

Vol 6 (02) ◽

pp. 07-12

Author(s):

Diksha Siddhamshittiwar

Keyword(s):

Average Power ◽

Full Adder ◽

Deep Submicron ◽

Power Reduction ◽

Vlsi Circuits ◽

Power Gating ◽

Static Power ◽

Simulation Results ◽

Efficient Power ◽

Standby Mode

Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

Download Full-text