scholarly journals SIGNAL-PATH-LEVEL DUAL-Vt ASSIGNMENT FOR LEAKAGE POWER REDUCTION

2006 ◽  
Vol 15 (02) ◽  
pp. 197-216 ◽  
Author(s):  
YU WANG ◽  
HUAZHONG YANG ◽  
HUI WANG
Keyword(s):  
Threshold Voltage ◽  
High Performance ◽  
Low Voltage ◽  
Power Reduction ◽  
Threshold Voltages ◽  
Fast Development ◽  
Static Power ◽  
Signal Path ◽  
Subcircuit Extraction ◽  
New Algorithms

Along with the fast development of dual-threshold voltage (dual-Vt) and multi-threshold technology, it is possible to use them to reduce static power in low-voltage high-performance circuits. In this paper, we propose a new method to realize CMOS digital circuits that are implemented with dual-Vt technology. We first present a new signal-path-level circuit model which effectively deals with the fact that there can be two threshold voltages assigned to a single gate. In order to assign proper threshold voltage to all the signal-paths in the circuit, our new algorithms introduce the concept of subcircuit extraction and include the hierarchy algorithms which are effective and fast. Experimental results show that our algorithms produce a significant reduction for the ISCAS85 benchmark circuits.

Leakage Power Reduction in 32-bit Digital Comparator Using Modified Power Gating Technique

2015 ◽  
Vol 742 ◽  
pp. 741-744 ◽  
Author(s):  
G. Amuthavalli ◽  
R. Gunasundari ◽  
A. Nijandan
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Channel Length ◽  
Power Reduction ◽  
Leakage Power ◽  
Power Gating ◽  
Dynamic Power ◽  
Digital Comparator ◽  
Static Power ◽  
Scaling Down

As scaling down of CMOS transistor’s channel length is done for miniaturization, the design community primarily focuses on the high performance & power-aware design. The power consumption of any circuit solely holds the performance and the life of it. But static power consumption deteriorates them and dominates the dynamic power consumption because of its leakage components. A modified approach of pulse triggering in the Power Gating technique called MPG (Modified Power Gating) is proposed to reduce the static power consumption (leakage power) of digital subsystems. Sub threshold leakage power of MPG Inverter (INV) and 32-bit Digital Comparator (DC) is analyzed and reduced with 35% to 40% leakage savings compared with conventional and existing techniques by simulating it in Cadence GPDK.

scholarly journals A REVIEW OF LOW VOLTAGE AND LOW POWER CMOS ADDERS USING VLSI DESIGN IN VERILOG/VHDL

2021 ◽  
Vol 6 (3) ◽  
Author(s):  
Lokesh S
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Vlsi Design ◽  
Research Field ◽  
Look Ahead ◽  
Threshold Voltages ◽  
Ripple Carry Adder

The dominant portion of power dissipation in CMOS adder circuits, due to logic transitions, varies as the square of the supply, significant savings in power dissipation may be exacted by operating with reduced supply voltage. If the supply voltage is reduced while threshold voltage stays same, the noise margins will reduce. Addition is a crucial process because it usually involve carry ripple steps which must propagate a carry signal from each bit to it’s higher bit position. This results in a substantial circuit delay. The adder which lies in the crucial delay path will effectively determine the system overall speed. To improve noise margins, the threshold voltages must also be made smaller. However subthreshold leakage current increases exponentially when threshold voltage is reduced. The higher static dissipation may then offset the reduction in transitions portion of the dissipation. Hence the devices needed to have threshold voltages that maximizes the net reduction in the dissipation. Addition is an obligatory operation that is crucial to processing the fundamental arithmetic operations. Due to the potential versatility of adders in this contemporary research field, the existing adders and adder designs currently intended for future low voltage and low power environments. This can be achieved by the CMOS adders namely Parallel Adder, Ripple Carry Adder(RCA), Carry Look Ahead Adder(CLA), Carry Select Adder(CSL), Carry Save Adder(CSA), Carry Skip Adder(CSK), Conditional Sum Adder(COS).

High-Performance Damascene-Gate Thin Film Transistors

1999 ◽  
Vol 557 ◽  
Author(s):  
Eugene Ma ◽  
Sigurd Wagner
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Field Effect ◽  
High Performance ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Linear Region ◽  
Threshold Voltages ◽  
Bottom Gate

AbstractWe report a novel TFT structure where the gate metal is embedded into a SiNx passivation layer. This allows the subsequent gate dielectric layer to be much thinner than in conventional bottom-gate structures. thereby reducing the threshold voltage and the sub-threshold slope. TFTs employing these damascene-gate structures were fabricated with SiNX gate dielectrics as thin as 50 nm. Such devices exhibit threshold voltages of 0.9 V, sub-threshold slopes of 0.1 V/dec, ION/IOFF current ratios of 106 and linear region field-effect mobilities of 0.6 cm2/Vs.

scholarly journals High-Linearity Self-Biased CMOS Current Buffer

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 423
Author(s):  
Javier Martínez-Nieto ◽  
María Sanz-Pascual ◽  
Nicolás Medrano-Marqués ◽  
Belén Calvo-López ◽  
Arturo Sarmiento-Reyes
Keyword(s):  
High Performance ◽  
Simple Structure ◽  
Low Voltage ◽  
Harmonic Distortion ◽  
Input Resistance ◽  
Cmos Process ◽  
Output Current ◽  
Current Ratio ◽  
Class Ab ◽  
Static Power

A highly linear fully self-biased class AB current buffer designed in a standard 0.18 μ m CMOS process with 1.8 V power supply is presented in this paper. It is a simple structure that, with a static power consumption of 48 μ W, features an input resistance as low as 89 Ω , high accuracy in the input–output current ratio and total harmonic distortion (THD) figures lower than −60 dB at 30 μ A amplitude signal and 1 kHz frequency. Robustness was proved through Monte Carlo and corner simulations, and finally validated through experimental measurements, showing that the proposed configuration is a suitable choice for high performance low voltage low power applications.

scholarly journals Subthreshold Characteristics of AlGaN/GaN MIS-FinFETs with Controlling Threshold Voltages

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1967
Author(s):  
Quan Dai ◽  
Jung-Hee Lee
Keyword(s):  
Threshold Voltage ◽  
Dielectric Layer ◽  
Low Voltage ◽  
Field Effect Transistors ◽  
Power Switching ◽  
Threshold Voltages ◽  
Voltage Dependent ◽  
Standby Power ◽  
20 Nm ◽  
Efficient Power

AlGaN/GaN metal-insulator-semiconductor field-effect transistors with fin structures (AlGaN/GaN MIS-FinFETs) were fabricated and characterized by changing fin width and using different dielectric layers. The FinFET with 20 nm-thick SiO2 dielectric layer exhibits a very small subthreshold swing (SS) of 56 mV/decade. However, the threshold voltage of the device is too low to ensure low off-state leakage current (at the gate voltage of 0 V), even though the fin width of the device is reduced to 30 nm, which would not meet the requirement for low standby power consumption. On the other hand, the FinFET with a 10 nm-thick Al2O3 dielectric layer and a much wider fin width of 100 nm shows normally-off operation with a threshold voltage of 0.8 V, SS of 63 mV/dec, and very low off-state current of 1 nA/mm. When the fin width is reduced to 40 nm, the threshold voltage of the FinFET is increased to 2.3 V and the SS is decreased to 52 mV/decade. These excellent switching performances convince us that the FinFETs might be promising either for low voltage logic or for efficient power switching applications. The observed SS values, which are smaller than the theoretical Boltzmann limit (60 mV/decade), can be explained by the concept of the voltage-dependent effective channel width.

scholarly journals Low-Voltage Cathodoluminescent Properties of Europium-Activated Anion-Deficient Fluorites

1994 ◽  
Vol 348 ◽  
Author(s):  
Mark T. Anderson ◽  
Mark L. F. Phillips ◽  
Robert J. Walko
Keyword(s):  
Particle Size ◽  
Transition Metal ◽  
Particle Size Distribution ◽  
Size Distribution ◽  
Threshold Voltage ◽  
Applied Voltage ◽  
Low Voltage ◽  
Luminous Efficiency ◽  
Photoluminescence Spectra ◽  
Threshold Voltages

ABSTRACTWe have examined the optical bandgap, particle size distribution, photoluminescence spectra, and cathodoluminescent response of fifteen phosphors that contain transition-metal and main-group sensitizers. We determined luminance versus applied voltage curves for electron energies from 5 to 1000 eV. Seven phosphors exhibit threshold voltages less than 110 V. Y1.96Eu0.04O3 exhibits a threshold voltage of 13 V and, at 300 V, displays a luminance of 25 fL and a luminous efficiency of 0.02 lm/W.

Current State of Biological High-Resolution Scanning Electron Microscopy

1988 ◽  
Vol 46 ◽  
pp. 180-181 ◽  
Author(s):  
Klaus-Ruediger Peters
Keyword(s):  
High Performance ◽  
Low Voltage ◽  
Backscattered Electrons ◽  
Lens Position ◽  
Low Voltage Operation ◽  
Signal Collection ◽  
Probe Size ◽  
Electron Microscopes ◽  
Scanning Electron Microscopes ◽  
Scanning Electron

A new generation of high performance field emission scanning electron microscopes (FSEM) is now commercially available (JEOL 890, Hitachi S 900, ISI OS 130-F) characterized by an "in lens" position of the specimen where probe diameters are reduced and signal collection improved. Additionally, low voltage operation is extended to 1 kV. Compared to the first generation of FSEM (JE0L JSM 30, Hitachi S 800), which utilized a specimen position below the final lens, specimen size had to be reduced but useful magnification could be impressively increased in both low (1-4 kV) and high (5-40 kV) voltage operation, i.e. from 50,000 to 200,000 and 250,000 to 1,000,000 x respectively.At high accelerating voltage and magnification, contrasts on biological specimens are well characterized1 and are produced by the entering probe electrons in the outmost surface layer within -vl nm depth. Backscattered electrons produce only a background signal. Under these conditions (FIG. 1) image quality is similar to conventional TEM (FIG. 2) and only limited at magnifications >1,000,000 x by probe size (0.5 nm) or non-localization effects (%0.5 nm).

Transient self back-biased buffer for low-voltage high-performance applications in standard CMOS technologies

1999 ◽  
Vol 35 (2) ◽  
pp. 112 ◽  
Author(s):  
Y. Moisiadis ◽  
I. Bouras ◽  
C. Papadas ◽  
J.-P. Schoellkopf
Keyword(s):  
High Performance ◽  
Low Voltage
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