scholarly journals Boundary Scan Architecture for a Double Precision Floating Point Subtractor

2021 ◽  
Vol 23 (06) ◽  
pp. 521-529
Author(s):  
Anirudh Kashyap ◽  
◽  
Kusuma Keerthi ◽  
Dr. Shilpa D.R. ◽  
◽  
...  
Keyword(s):  
System On Chip ◽  
Floating Point ◽  
Double Precision ◽  
Boundary Scan ◽  
The Core ◽  
Action Group ◽  
On Chip ◽  
Made In ◽  
Inputs And Outputs

The boundary scan logic for testing was developed in order to make the process of testing easier for System-on-Chip (SoC) [1] architectures. The proposed work focuses on designing a boundary scan logic for a 64-bit floating-point subtractor unit. The TAP controller designed is capable of executing the three mandatory Joint Test Action Group (JTAG) instructions of the IEEE 1149 standard. The testing architecture has the potential to not only test the functionality of the core logic but also to test single stuck-at faults for all the inputs and outputs of the core logic. A provision for bypassing the core logic was made in order to skip the IC while testing numerous ICs together. A simulation was also performed to demonstrate the above procedures. The designed module can further be used in a larger circuit with other ICs [2]containing a similar boundary scan structure with individual TAP controllers.

Design of a Reconfigurable Coprocessor for Double Precision Floating Point Matrix Algorithms

2011 ◽  
Vol 58-60 ◽  
pp. 1037-1042
Author(s):  
Sheng Long Li ◽  
Zhao Lin Li ◽  
Qing Wei Zheng
Keyword(s):  
High Performance ◽  
Cmos Technology ◽  
General Purpose ◽  
Floating Point ◽  
Double Precision ◽  
Synthesis Time ◽  
Matrix Algorithms ◽  
Matrix Operations ◽  
On Chip ◽  
Software Execution

Double precision floating point matrix operations are wildly used in a variety of engineering and scientific computing applications. However, it’s inefficient to achieve these operations using software approaches on general purpose processors. In order to reduce the processing time and satisfy the real-time demand, a reconfigurable coprocessor for double precision floating point matrix algorithms is proposed in this paper. The coprocessor is embedded in a Multi-Processor System on Chip (MPSoC), cooperates with an ARM core and a DSP core for high-performance control and calculation. One algorithm in GPS applications is taken for example to illustrate the efficiency of the coprocessor proposed in this paper. The experiment result shows that the coprocessor can achieve speedup a factor of 50 for the quaternion algorithm of attitude solution in inertial navigation application compare with software execution time of a TI C6713 DSP. The coprocessor is implemented in SMIC 0.13μm CMOS technology, the synthesis time delay is 9.75ns, and the power consumption is 63.69 mW when it works at 100MHz.

scholarly journals SoC opportunities for boosting SDR GNSS performance

2019 ◽  
pp. 457-462
Author(s):  
A A Kumarin ◽  
I A Kudryavtsev
Keyword(s):  
Signal Processing ◽  
Computational Complexity ◽  
Embedded Systems ◽  
Software Defined Radio ◽  
System On Chip ◽  
Floating Point ◽  
Computational Performance ◽  
Gnss Receivers ◽  
On Chip ◽  
High Flexibility

Software-defined-radio (SDR) becomes an attractive technique for the development of GNSS receivers due to universal hardware and high flexibility. However, the performance of signal processing can be a challenging task. Real-time mode implementation requires fast floating point calculations in several threads, not available for most part of embedded systems. This paper describes the system-on-chip based device drastically increasing computational performance. A summary of computational complexity of each stage of GNSS receiver is provided and several particular solutions are proposed.

Analysis of Area and Delay for Floating Point Matrix Multiplication

2018 ◽  
Vol 15 (2) ◽  
pp. 621-626
Author(s):  
Y. R. Annie Bessant ◽  
T. Latha
Keyword(s):  
Matrix Multiplication ◽  
Optimal Choice ◽  
Floating Point ◽  
Design Parameters ◽  
Double Precision ◽  
Verilog Hdl ◽  
Delay Minimization ◽  
Processing Elements ◽  
Floating Point Number ◽  
On Chip

In this paper, a new area and delay minimization architecture is proposed for rank-1 update matrix–matrix multiplication whose inputs are double precision floating point number. The architecture design is based on pipelined multiplication which handles matrix of arbitrary sizes; the processing data are stored in dedicated on-chip BRAM. This minimization is introduced to designers as a trade-off between bandwidth and local memory. Analysis is presented for the design parameters optimal choice. In addition, Vedic matrix multiplication architecture is given in order to explore the variations in power, delay and memory. The hardware architecture is described in Verilog HDL synthesized for a family virtex-6 and device xc6vlx240t FPGA, which scale more than 40 processing elements. Various parameters like LUTs, Slices, bonded IOBs, frequency, DSP48E1S, delay, Power, CPU Completion time and Memory usage are analysed. Rank 1 update consumes a power of 2.520 watt and has a delay of 5.277 ns respectively. Comparing other rank-1 multiplication methods our proposed algorithms uses 15% less area resources and improves the delay in 12%.

scholarly journals High-Performance Time Server Core for FPGA System-on-Chip

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 528 ◽  
Author(s):  
Julian Viejo ◽  
Jorge Juan-Chico ◽  
Manuel J. Bellido ◽  
Paulino Ruiz-de-Clavijo ◽  
David Guerrero ◽  
...  
Keyword(s):  
High Performance ◽  
System On Chip ◽  
The Core ◽  
Performance Time ◽  
Network Time ◽  
Wide Range ◽  
Network Time Protocol ◽  
Field Programmable ◽  
And Performance ◽  
On Chip

This paper presents the complete design and implementation of a low-cost, low-footprint, network time protocol server core for field programmable gate arrays. The core uses a carefully designed modular architecture, which is fully implemented in hardware using digital circuits and systems. Most remarkable novelties introduced are a hardware-optimized timekeeping algorithm implementation, and a full-hardware protocol stack and automatic network configuration. As a result, the core is able to achieve similar accuracy and performance to typical high-performance network time protocol server equipment. The core uses a standard global positioning system receiver as time reference, has a small footprint and can easily fit in a low-range field-programmable chip, greatly scaling down from previous system-on-chip time synchronization systems. Accuracy and performance results show that the core can serve hundreds of thousands of network time clients with negligible accuracy degradation, in contrast to state-of-the-art high-performance time server equipment. Therefore, this core provides a valuable time server solution for a wide range of emerging embedded and distributed network applications such as the Internet of Things and the smart grid, at a fraction of the cost and footprint of current discrete and embedded solutions.

Overcoming the Challenges of Porting OpenCV to TI's Embedded ARM + DSP Platforms

2012 ◽  
Vol 49 (3) ◽  
pp. 260-274 ◽  
Author(s):  
Joseph Coombs ◽  
Rahul Prabhu ◽  
Greg Peake
Keyword(s):  
Digital Signal Processor ◽  
Digital Signal ◽  
Academic Community ◽  
System On Chip ◽  
Floating Point ◽  
Software Packages ◽  
Functional Development ◽  
On Chip ◽  
Algorithm Implementation ◽  
Memory Constraints

The growing performance and decreasing price of embedded processors are opening many doors, for both developers in the industry and in academia. However, the complexities of these systems can create serious developmental bottlenecks. Sophisticated software packages such as OpenCV can assist in both the functional development and educational aspects of these otherwise complex applications; such tools lend themselves very well to use by the academic community, in particular in providing examples of algorithm implementation. However the task of migrating this software to embedded platforms poses its own challenges. This paper will review how to mitigate some of these issues, including C++ implementation, memory constraints, floating-point support, and opportunities to maximise performance using vendor-optimised libraries and integrated accelerators or co-processors. Finally, we will introduce a new effort by Texas Instruments to optimise vision systems by running OpenCV on the C6000™ digital signal processor architecture. Benchmarks will show the advantage of using the DSP by comparing the performance of a DSP+ARM® system-on-chip (SoC) processor against an ARM-only device.

Will Love Tear Us Apart: Adapting the Lyrical to the Ludic

CounterText ◽  
2016 ◽  
Vol 2 (2) ◽  
pp. 217-235
Author(s):  
Gordon Calleja
Keyword(s):  
Design Process ◽  
Game Design ◽  
Digital Games ◽  
Design Decisions ◽  
The Core ◽  
Lyrical Poetry ◽  
Insight Into ◽  
Made In

This paper gives an insight into the design process of a game adaptation of Joy Division's Love Will Tear Us Apart (1980). It outlines the challenges faced in attempting to reconcile the diverging qualities of lyrical poetry and digital games. In so doing, the paper examines the design decisions made in every segment of the game with a particular focus on the tension between the core concerns of the lyrical work being adapted and established tenets of game design.

Multiprocessor transport surveillance video system based on "system on chip" technology

2020 ◽  
Author(s):  
Ш.С. Фахми ◽  
Н.В. Шаталова ◽  
В.В. Вислогузов ◽  
Е.В. Костикова
Keyword(s):  
System On Chip ◽  
Reference Points ◽  
Surveillance Video ◽  
Video Information ◽  
Chip Technology ◽  
Intelligent Video Surveillance System ◽  
Speed Up ◽  
Algorithmic Analysis ◽  
Computational Procedures ◽  
On Chip

В данной работе предлагаются математический аппарат и архитектура многопроцессорной транспортной системы на кристалле (МПТСнК). Выполнена программно-аппаратная реализация интеллектуальной системы видеонаблюдения на базе технологии «система на кристалле» и с использованием аппаратного ускорителя известного метода формирования опорных векторов. Архитектура включает в себя сложно-функциональные блоки анализа видеоинформации на базе параллельных алгоритмов нахождения опорных точек изображений и множества элементарных процессоров для выполнения сложных вычислительных процедур алгоритмов анализа с использованием средств проектирования на базе реконфигурируемой системы на кристалле, позволяющей оценить количество аппаратных ресурсов. Предлагаемая архитектура МПТСнК позволяет ускорить обработку и анализ видеоинформации при решении задач обнаружения и распознавания чрезвычайных ситуаций и подозрительных поведений. In this paper, we propose the mathematical apparatus and architecture of a multiprocessor transport system on a chip (MPTSoC). Software and hardware implementation of an intelligent video surveillance system based on the "system on chip" technology and using a hardware accelerator of the well-known method of forming reference vectors. The architecture includes complex functional blocks for analyzing video information based on parallel algorithms for finding image reference points and a set of elementary processors for performing complex computational procedures for algorithmic analysis. using design tools based on a reconfigurable system on chip that allows you to estimate the amount of hardware resources. The proposed MPTSoC architecture makes it possible to speed up the processing and analysis of video information when solving problems of detecting and recognizing emergencies and suspicious behaviors

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