scholarly journals Towards a generic operational amplifier with dynamic reconfiguration capability

2006 ◽  
Vol 4 ◽  
pp. 259-262
Author(s):  
S. K. Lakshmanan ◽  
A. Koenig
Keyword(s):  
Operational Amplifier ◽  
Building Blocks ◽  
Cmos Technology ◽  
Mixed Signal ◽  
Programmable Analog ◽  
Single Instance ◽  
Field Programmable ◽  
Block Level ◽  
Industrial Standards ◽  
The Impact

Abstract. Analog and analog-digital mixed signal electronics needed for sensor systems are indispensable components which tend to drifts from the normal phase of operation due to the impact of manufacturing conditions and environmental influences like etching, aging etc. Precise design methodology, trimming / calibration are essential to restore functionality of the system. Recent block level granular approaches using Field Programmable Analog Array and the more recent approaches from evolutionary electronics providing transistor level granularity using Field Programmable Transistor Arrays offers considerable extensions. In our work, we started on a new medium granular level approach called Field Programmable medium-granular Mixed-signal Array (FPMA) providing basic building blocks of heterogeneous array of active and passive devices to configure established circuit structures which are adaptive, biologically inspired and dynamically re-configurable. Our design objective is to create components of clear compatibility to that of the industrial standards having predictable behavior along with the incorporation of existing design knowledge. The cells can be used in as a single instance or multiple instances. Further, we will focus on a generic dynamic reconfigurable amplifier cell with flexible topology and dimension called Generic Operational Amplifier (GOPA). The incentive of our work comes from recent development in the field of measurement and instrumentation. The digital programming of analog devices is carried out using range of algorithms from simple to evolutionary. Physical realization of the basic cells is carried out in 0.35 μm CMOS technology.

Rapid prototyping of algorithmic A/D converters based on FPAA devices

2013 ◽  
Vol 61 (3) ◽  
pp. 691-696 ◽  
Author(s):  
R. Suszynski ◽  
K. Wawryn
Keyword(s):  
Rapid Prototyping ◽  
Sinusoidal Signal ◽  
Digital Converter ◽  
Mixed Signal ◽  
Analog Digital Converter ◽  
Signal Systems ◽  
Programmable Analog ◽  
Field Programmable ◽  
Field Programmable Analog Array

Abstract A rapid prototyping method for designing mixed signal systems has been presented in the paper. The method is based on implementation of the field programmable analog array (FPAA) to configure and reconfigure mixed signal systems. A serial algorithmic analog digital converter has been used as an example. Three converter architectures have been selected and implemented FPAA device. To verify and illustrate converters operation and prototyping capabilities, implemented converters have been excited by a sinusoidal signal. Analog sinusoidal excitations, digital responses and sinusoidal waveforms after reconstruction are presented.

IMPLEMENTATION ISSUES FOR HIGH-BANDWIDTH FIELD-PROGRAMMABLE ANALOG ARRAYS

1998 ◽  
Vol 08 (05n06) ◽  
pp. 541-558 ◽  
Author(s):  
VINCENT C. GAUDET ◽  
P. GLENN GULAK
Keyword(s):  
Cmos Technology ◽  
Current Conveyor ◽  
Test Results ◽  
Programmable Analog ◽  
Field Programmable ◽  
High Bandwidth ◽  
Field Programmable Analog Arrays ◽  
Analog Arrays ◽  
A Current ◽  
Field Programmable Analog Array

This paper is a tutorial introduction to field-programmable analog arrays, as well as a review of existing field-programmable analog array architectures, of both educational and industrial origin. Circuit issues relevant to the development of high-bandwidth FPAAs are presented. A current conveyor-based architecture, which promises to achieve video bandwidths, is described. Test results are presented for the CMOS current conveyor-based FPAA building block, with programmable transconductors and capacitors. Measurements indicate bandwidths in excess of 10 MHz, and functionality of amplifiers, integrators, differentiators, and adders. The die area is 1.5 mm× 3.5 mm in a 0.8 μm CMOS technology.

scholarly journals Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design

2017 ◽  
Vol 27 (03n04) ◽  
pp. 1750006 ◽  
Author(s):  
Farhad Merchant ◽  
Anupam Chattopadhyay ◽  
Soumyendu Raha ◽  
S. K. Nandy ◽  
Ranjani Narayan
Keyword(s):  
Linear Algebra ◽  
High Performance ◽  
Graphics Processing Unit ◽  
Building Blocks ◽  
General Purpose ◽  
Performance Tuning ◽  
Floating Point ◽  
Processing Unit ◽  
Field Programmable ◽  
The Impact

Basic Linear Algebra Subprograms (BLAS) and Linear Algebra Package (LAPACK) form basic building blocks for several High Performance Computing (HPC) applications and hence dictate performance of the HPC applications. Performance in such tuned packages is attained through tuning of several algorithmic and architectural parameters such as number of parallel operations in the Directed Acyclic Graph of the BLAS/LAPACK routines, sizes of the memories in the memory hierarchy of the underlying platform, bandwidth of the memory, and structure of the compute resources in the underlying platform. In this paper, we closely investigate the impact of the Floating Point Unit (FPU) micro-architecture for performance tuning of BLAS and LAPACK. We present theoretical analysis for pipeline depth of different floating point operations like multiplier, adder, square root, and divider followed by characterization of BLAS and LAPACK to determine several parameters required in the theoretical framework for deciding optimum pipeline depth of the floating operations. A simple design of a Processing Element (PE) is presented and shown that the PE outperforms the most recent custom realizations of BLAS and LAPACK by 1.1X to 1.5X in GFlops/W, and 1.9X to 2.1X in Gflops/mm2. Compared to multicore, General Purpose Graphics Processing Unit (GPGPU), Field Programmable Gate Array (FPGA), and ClearSpeed CSX700, performance improvement of 1.8-80x is reported in PE.

Research of a Mixed-Signal Programmable SoC Based on FPAA

2014 ◽  
Vol 556-562 ◽  
pp. 1741-1744
Author(s):  
Jun Deng ◽  
Hua Yong Tan ◽  
Lun Cai Liu ◽  
Lin Tao Liu
Keyword(s):  
Digital Signal ◽  
Intermediate Frequency ◽  
Mixed Signal ◽  
Programmable Analog ◽  
Baseband Signal ◽  
Field Programmable ◽  
Baseband Signal Processing ◽  
Good Potential ◽  
On Chip ◽  
Field Programmable Analog Array

This paper presents a novel architecture for mixed-signal SoC, which integrates a Field Programmable Analog Array (FPAA) into a SoC based on 32-bit RISC CPU. The FPAA unit can be configured as Filter, Comparator, Gain Amplifier, and so on. The proposed mixed-signal SoC can transform the intermediate frequency (IF) analog signal to baseband digital signal and realize the real-time baseband signal processing, besides this, which can transmit the modulated IF signals which are converted from baseband signals by digital up-conversion (DUC). The proposed mixed-signal SoC is a transceiver on chip actually, due to the internal integrated IPs, such as ADC, DAC, DDC and DUC, which can provide smaller board area, lower power consumption and the system cost for the product development of transceiver. This design will have a good potential for wireless communication applications.

scholarly journals A New Universal Second-Order Filter using Configurable Analog Building Blocks (CABs) for Filed-Programmable Analogue Arrays

2011 ◽  
Vol 7 (2) ◽  
pp. 83
Author(s):  
M. T. Abuelma'atti ◽  
O. O. Fares
Keyword(s):  
High Frequency ◽  
Building Blocks ◽  
Second Order ◽  
Spice Simulation ◽  
Bipolar Junction Transistor ◽  
Order Filter ◽  
Programmable Analog ◽  
Field Programmable ◽  
Junction Transistor ◽  
Analog Arrays

 In this paper, the design of a universal second-order filter using configurable analog blocks (CABs) for field programmable analog arrays is presented. The configurable blocks are capable of performing integration, differentiation, amplification, log, anti-log, add and negate functions. To maintain high frequency operation, the programmability and configurability of the blocks are achieved by digitally modifying the block's biasing conditions. Using at most four CABs, this article shows that it is possible to design a versatile second-order filter realizing all the standard five filter functions; lowpass, highpass, bandpass, notch and allpass. SPICE simulation results using practical bipolar junction transistor (BJT) parameters confirm the feasibility of using the CABs in designing second-order filters. 

MOS-C TOW-THOMAS FILTER USING VOLTAGE OP AMP, CURRENT FEEDBACK OP AMP AND OPERATIONAL TRANSRESISTANCE AMPLIFIER

2009 ◽  
Vol 18 (01) ◽  
pp. 151-179 ◽  
Author(s):  
AHMED M. SOLIMAN ◽  
AHMED H. MADIAN
Keyword(s):  
Operational Amplifier ◽  
Building Blocks ◽  
Detailed Comparison ◽  
Cmos Technology ◽  
Spice Simulation ◽  
Current Feedback ◽  
Op Amp ◽  
Operational Transresistance Amplifier ◽  
Current Voltage ◽  
Current Feedback Operational Amplifier

Several MOS-C realizations of the Tow-Thomas circuit using the commercially available voltage operational amplifier and the current feedback operational amplifier are reviewed in this paper. Additional MOS-C Tow-Thomas realizations using the operational transresistance amplifier and the differential current voltage conveyor are also included. MOS-C realizations of the Tow-Thomas circuit using CMOS operational amplifier, CMOS current feedback operational amplifier and CMOS operational transresistance amplifier are also given. Spice simulation results using 0.18 CMOS technology model from MOSIS are included together with detailed comparison tables to demonstrate the differences between MOS-C Tow-Thomas circuits using both of the commercially available active building blocks and CMOS integrated building blocks.

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