scholarly journals A Nonuniform Reference Voltage Optimization Based on Relative-Precision-Loss Ratios in MLC NAND Flash Memory

2021 ◽  
Vol 14 (2) ◽  
pp. 75
Author(s):  
Caifeng Lv ◽  
Xiujie Huang ◽  
Shancheng Zhao

In Multi-Level-Cell (MLC) NAND flash memory, cell-to-cell interference (CCI) and retention time have become the main noise that degrades the data storage reliability. To mitigate such noise, a relative precision loss (RPL) nonuniform reference voltage sensing strategy is proposed in this paper. First, based on the NAND flash channel model with CCI and retention noise, we simulate the data storage process of MLC NAND flash by Monte Carlo method, and find that the threshold-voltage of each disturbed storage state shows approximately to be Gaussian distributed. Then, by Gaussian approximation, the distribution of threshold voltage can be estimated easily in mathematics with a little loss. Second, we introduce a concept of log-likelihood ratio (LLR)-based RPL ratio to determine the dominating overlap regions, and then propose a new nonuniform reference voltage sensing strategy. This strategy does not only reduce the memory sensing precision (i.e., the number of reference voltages), but also maintains the reliability of the soft information of NAND flash memory channel output for soft decoding. Third, we implement extensive simulations to verify the performance of the new nonuniform sensing strategy. The BER performances of LDPC codes for different sensing strategies are provided to show that the proposed LLR-based RPL-nonuniform sensing strategy can make a good compromise between memory sensing latency and error-correction performance.

2014 ◽  
Vol 513-517 ◽  
pp. 2094-2098 ◽  
Author(s):  
Wen Zhe Zhao ◽  
Kai Zhao ◽  
Qiu Bo Chen ◽  
Min Jie Lv ◽  
Zuo Xun Hou

This paper concerns the design of high-speed and low-cost LDPC code bit-flipping decoder. Due to its inferior error correction strength, bit-flipping decoding received very little attention compared with message-passing decoding. Nevertheless, emerging flash-based solid-state data storage systems inherently favor a hybrid bit-flipping/message-passing decoding strategy, due to the significant dynamics and variation of NAND flash memory raw storage reliability. Therefore, for the first time highly efficient silicon implementation of bit-flipping decoder becomes a practically relevant topic. To address the drawbacks caused by the global search operation in conventional bit-flipping decoding, this paper presents a novel bit-flipping decoder design. Decoding simulations and ASIC design show that the proposed design solution can achieve upto 80% higher decoding throughput and meanwhile consume upto 50% less silicon cost, while maintaining almost the same decoding error correction strength.


2020 ◽  
Vol 8 ◽  
pp. 140-144 ◽  
Author(s):  
Tao Yang ◽  
Zhiliang Xia ◽  
Dandan Shi ◽  
Yingjie Ouyang ◽  
Zongliang Huo

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