Low-Noise and High-Frequency 0.10μm body-tied SOI-CMOS Technology with High-Resistivity Substrate for Low-Power 10Gbps Network LSI

2003 ◽  
Author(s):  
Toshiaki Iwamatsu ◽  
Mikio Tujiuchi ◽  
Yuuichi Hirano ◽  
Takuji Matsumoto ◽  
Hiroyuki Takashino ◽  
...  
Keyword(s):  
Low Power ◽  
High Frequency ◽  
Cmos Technology ◽  
Low Noise ◽  
High Resistivity ◽  
Soi Cmos

scholarly journals A 4-mW Temperature-Stable 28 GHz LNA with Resistive Bias Circuit for 5G Applications

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1225
Author(s):  
Dongze Li ◽  
Qingzhen Xia ◽  
Jiawei Huang ◽  
Jinwei Li ◽  
Hudong Chang ◽  
...  
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Silicon On Insulator ◽  
Gain Variation ◽  
Measurement Results ◽  
Noise Amplifier ◽  
Bias Point ◽  
Soi Cmos

This paper presents a low power two-stage single-end (SE) 28 GHz low-noise amplifier (LNA) in 90 nm silicon-on-insulator (SOI) CMOS technology for 5G applications. In this design, the influence of bias circuit is discussed. The 1200 Ω resistor which was adopted in bias circuit can feed DC voltage as well as keep whole circuit unconditionally stable. The gate bias points are set to 0.55 V to make the circuit low-power and temperature-stable. Measurement results illustrated that the LNA achieved a maximum small signal gain of 18.1 dB and an average 3.1 dB noise figure (NF) in operating frequency band. Measured S11 was below −10 dB between 25 GHz and 29 GHz and reverse isolation S12 was below −25 dB throughout the band. It consumed only 4 mW by proper selection of bias point with core area of 0.16 mm2 without pads. The fabricated LNA has demonstrated a gain variation of 3 dB and a NF variation of 1.9 dB from −40 °C to 125 °C with power variation of 0.8 mW. It suggests that the proposed SOI CMOS LNA can be a promising candidate for 5G applications.

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

High-Count Rate, Low Power and Low Noise Single Electron Readout ASIC in 65nm CMOS Technology

2021 ◽  
Author(s):  
Matthew Al Disi ◽  
Alireza Mohammad Zaki ◽  
Qinwen Fan ◽  
Stoyan Nihtianov
Keyword(s):  
Low Power ◽  
Count Rate ◽  
Cmos Technology ◽  
Low Noise ◽  
Single Electron ◽  
High Count ◽  
High Count Rate

scholarly journals Design of Low Power UWB CMOS Low Noise Amplifier using Active Inductor for WLAN Receiver

2018 ◽  
Vol 7 (2.24) ◽  
pp. 448
Author(s):  
S Manjula ◽  
M Malleshwari ◽  
M Suganthy
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Wide Band ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Design System ◽  
Active Inductor ◽  
Chip Area ◽  
Noise Amplifier

This paper presents a low power Low Noise Amplifier (LNA) using 0.18µm CMOS technology for ultra wide band (UWB) applications. gm boosting common gate (CG) LNA is designed to improve the noise performance.  For the reduction of on chip area, active inductor is employed at the input side of the designed LNA for input impedance matching. The proposed UWB LNA is designed using Advanced Design System (ADS) at UWB frequency of 3.1-10.6 GHz. Simulation results show that the gain of 10.74+ 0.01 dB, noise figure is 4.855 dB, input return loss <-13 dB and 12.5 mW power consumption.  

scholarly journals A Low-Power Opamp-Less Second-Order Delta-Sigma Modulator for Bioelectrical Signals in 0.18 µm CMOS

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6456
Author(s):  
Fernando Cardes ◽  
Nikhita Baladari ◽  
Jihyun Lee ◽  
Andreas Hierlemann
Keyword(s):  
Low Power ◽  
Low Frequency ◽  
Cmos Technology ◽  
Low Noise ◽  
Second Order ◽  
Frequency Noise ◽  
Voltage Controlled Oscillator ◽  
Noise Shaping ◽  
Delta Sigma Modulator ◽  
Delta Sigma

This article reports on a compact and low-power CMOS readout circuit for bioelectrical signals based on a second-order delta-sigma modulator. The converter uses a voltage-controlled, oscillator-based quantizer, achieving second-order noise shaping with a single opamp-less integrator and minimal analog circuitry. A prototype has been implemented using 0.18 μm CMOS technology and includes two different variants of the same modulator topology. The main modulator has been optimized for low-noise, neural-action-potential detection in the 300 Hz–6 kHz band, with an input-referred noise of 5.0 μVrms, and occupies an area of 0.0045 mm2. An alternative configuration features a larger input stage to reduce low-frequency noise, achieving 8.7 μVrms in the 1 Hz–10 kHz band, and occupies an area of 0.006 mm2. The modulator is powered at 1.8 V with an estimated power consumption of 3.5 μW.

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