scholarly journals A Bulk-Driven Quasi-Floating Gate Regulated Cascode Current Mirror and Its Application in Squarer Circuit

2022 ◽  
Author(s):  
bchir bchir ◽  
Mounira Bchir ◽  
Imen Aloui ◽  
Nejib Hassen
Keyword(s):  
Performance Improvement ◽  
Supply Voltage ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Floating Gate ◽  
Input Current ◽  
Current Mirror ◽  
Transfer Error ◽  
Simulation Results ◽  
Cascode Current Mirror

Abstract A regulated cascode current mirror (RGC) and its improved version with bulk driven quasi floating gate technique (BD-QFG) are presented in this paper. The proposed BD-QFG RGC current mirror (CM) is compared with the conventional (GD) RGC CM to show the performance improvement. The conventional and unconventional CM are implemented in Candace Virtuoso using 90 nm CMOS technology. For input current (Iin) varied from 0 to 200 μA and for 0.8 V supply voltage, the simulation results present that the proposed BD-QFG RGC CM has less variation in current transfer error (0.2%) as compared to the GD RGC CM (12%). The output voltage requirement for 200 µA input current is respectively 0.7 V and 0.17 V for the GD RGC CM and the BD-QFG RGC CM. The power consumption of the proposed circuit is 22.71 μW which is 0.15 μW higher than the GD RGC (22.56 μW). The total harmonic distortion (THD) of the proposed circuit is 0.4% which is 1.1% less than the conventional circuit (1.5%). All these improvements in the proposed BD-QFG RGC CM are attained at a cost of 0.05 GHz reduction in frequency (2.31 GHz). The minimum supply voltage of BD-QFG RGC CM and GD RGC CM is 0.4 V and

Low Power FGSRAM Cell Using Sleepy and LECTOR Technique

2016 ◽  
Vol 4 (2) ◽  
pp. 333 ◽  
Author(s):  
Kanan Bala Ray ◽  
Sushanta Kumar Mandal ◽  
Shivalal Patro
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Stability ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Floating Gate ◽  
Power Supply Voltage ◽  
Operation Analysis ◽  
Sram Cell ◽  
Simulation Results

<em>In this paper floating gate MOS (FGMOS) along with sleep transistor technique and leakage control transistor (LECTOR) technique has been used to design low power SRAM cell. Detailed investigation on operation, analysis and result comparison of conventional 6T, FGSRAM, FGSLEEPY, FGLECTOR and FGSLEEPY LECTOR has been done. All the simulations are done in Cadence Virtuoso environment on 45 nm standard CMOS technology with 1 V power supply voltage. Simulation results show that FGSLEEPY LECTOR SRAM cell consumes very low power and achieves high stability compared to conventional FGSRAM Cell</em>

A 12-pulse rectifier with passive harmonic reduction based on UIPT in more electric aircrafts

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Rohollah Abdollahi
Keyword(s):  
Power Factor ◽  
Harmonic Distortion ◽  
Cost Savings ◽  
Cost Effective ◽  
Industrial Applications ◽  
Input Current ◽  
New Combination ◽  
Content Type ◽  
Harmonic Reduction ◽  
Simulation Results

Purpose The purpose of this paper is to provide a T autotransformer based 12-pulse rectifier with passive harmonic reduction in more electric aircraft applications. The T autotransformer uses only two main windings which result in volume, space, size, weight and cost savings. Also, the proposed unconventional inter-phase transformer (UIPT) with a lower kVA rating (about 2.6% of the load power) compared to the conventional inter-phase transformer results in a more harmonic reduction. Design/methodology/approach To increase rating and reduce the cost and complexity of a multi-pulse rectifier, it is well known that the pulse number must be increased. In some practical cases, a 12-pulse rectifier (12PR) is suggested as a good solution considering its simple structure and low weight. But the 12PR cannot technically meet the standards of harmonic distortion requirements for some industrial applications, and therefore, they must be used with output filters. In this paper, a 12PR is suggested, which consists of a T autotransformer 12PR and a passive harmonic reduction (PHR) based on the UIPT at direct current (DC) link. Findings To show the advantage of this new combination over other solutions, simulation results are used, and then, a prototype is implemented to evaluate and verify the simulation results. The simulation and experimental test results show that the input current total harmonic distortion (THD) of the suggested 12PR with a PHR based on UIPT is less than 5%, which meets the IEEE 519 requirements. Also, it is shown that in comparison with other solutions, it is cost effective, and at the same time, its power factor is near unity, and its rating is 29.92% of the load rating. Therefore, it is obvious that the proposed rectifier is a practical solution for more electric aircrafts. Originality/value The contributions of this paper are summarized as follows. The suggested design uses a retrofit T autotransformer, which meets all technical constraints, and in comparison, with other options, has less rating, weight, volume and cost. In the suggested rectifier, a PHR based on UIPT at its dc link of 12PR is used, which has good technical capabilities and lower ratings. In the PHR based on UIPT, an IPT is used, which has an additional secondary winding and four diodes. This solution leads to a reduction in input current THD and conduction losses of diodes. In full load conditions, the input line current THD and power factor are 4% and 0.99, respectively. The THD is less than 5%, which satisfies IEEE-519 and DO-160G requirements.

New Schmitt Trigger with Controllable Hysteresis using Dual Control Gate-Floating Gate Transistor (DCG-FGT)

2013 ◽  
Vol 2 (1) ◽  
pp. 49
Author(s):  
Abderrezak Marzaki ◽  
V. Bidal ◽  
R. Laffont ◽  
W. Rahajandraibe ◽  
J-M. Portal ◽  
...  
Keyword(s):  
Low Voltage ◽  
Schmitt Trigger ◽  
Cmos Technology ◽  
Floating Gate ◽  
Dual Control ◽  
Switching Voltage ◽  
Voltage Range ◽  
Rail To Rail ◽  
Floating Gate Transistor ◽  
Simulation Results

This paper presents different low voltage adjustable CMOS Schmitt trigger using DCG-FGT transistor. Simple circuits are introduced to provide flexibility to program the hysteresic threshold in this paper. The hysteresis can be controlled accurately at a large voltage range. The proposed Schmitt trigger have been designed using 90nm 1.2V CMOS technology and simulated using Eldo with PSP device models. The simulation results show rail-to-rail operation and adjustable switching voltages <em>V<sub>TH- </sub></em>(low switching voltage) and <em>V<sub>TH+ </sub></em>(high switching voltage).

A High-Linear CMOS Down Conversion Mixer Using Adjusting the Second and Third-Order Harmonic in Transconductance Stage

2014 ◽  
Vol 24 (01) ◽  
pp. 1550002 ◽  
Author(s):  
Mina Amiri ◽  
Adib Abrishamifar
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Simulation ◽  
Cmos Technology ◽  
Conversion Gain ◽  
Third Order ◽  
Cmos Mixer ◽  
Simulation Results ◽  
Down Conversion ◽  
Pmos Transistor

In this paper a new high-linear CMOS mixer is proposed. A well-known low voltage CMOS multiplier structure is used for mixer application in this paper and its linearity is provided by adjusting the value of a resistor, sizing the aspect ratio of a PMOS transistor and adding a proper value of inductor at the input stage. In simulation, a supply voltage as low as 1 V is applied to the circuit. Simulation results of improved mixer in a 0.18-μm CMOS technology illustrate 14 dB increases in IIP3 and also an increase around 1.4 dB is obtained in conversion gain. Furthermore, additional components which are used for improving linearity would not increase the power consumption and area significantly.

A SIMPLE 1.5 V RAIL-TO-RAIL CMOS CURRENT CONVEYOR

2007 ◽  
Vol 16 (04) ◽  
pp. 627-639 ◽  
Author(s):  
VARAKORN KASEMSUWAN ◽  
WEERACHAI NAKHLO
Keyword(s):  
Power Dissipation ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Current Conveyor ◽  
Common Source ◽  
Output Stage ◽  
Circuit Performance ◽  
Rail To Rail ◽  
Source Follower ◽  
Transfer Error

A simple 1.5 V rail-to-rail CMOS current conveyor is presented. The circuit is developed based on a complementary source follower with a common-source output stage. The circuit is designed using a 0.13 μm CMOS technology and HSPICE is used to verify the circuit performance. The current conveyor exhibits low impedance at terminal X (7.2 Ω) and can drive ± 0.6 V to the 300 Ω with the total harmonic distortion of 0.55% at the operating frequency of 3 MHz. The voltage transfer error (between the Y and X terminals) and current transfer error (between the X and Y terminals) are small (-0.2 dB). The power dissipation and bandwidth are 532 μW and over 300 MHz, respectively.

scholarly journals Performance Between PFC Cuk and Bridgeless PFC Cuk Converter with Various Output Voltages

2019 ◽  
Vol 8 (2S2) ◽  
pp. 41-46
Keyword(s):  
Low Power ◽  
Power Factor ◽  
Single Phase ◽  
Harmonic Distortion ◽  
Input Current ◽  
Unity Power Factor ◽  
Cuk Converter ◽  
Maximum Current ◽  
Simulation Results ◽  
Power Application

This paper presents about the comparison between single-phase PFC Cuk converter and bridgeless PFC (BPFC) Cuk converter for low power application. This study attempts to investigate the characteristics of conventional and bridgeless PFC Cuk converter structures with three different output voltages and verified by the simulation results. The BPFC Cuk converter provides a lower Total Harmonic Distortion (THD) of input current than the conventional PFC Cuk converter. However, the conventional PFC Cuk converter has advantage of less maximum current stress at components compared to the BPFC Cuk converter. Conventional and BPFC Cuk converter can achieve an approximately unity power factor (PF).

Tunable CMOS Active Inductor Using Widlar Current Source

2018 ◽  
Vol 28 (02) ◽  
pp. 1950027 ◽  
Author(s):  
Dhara P Patel ◽  
Shruti Oza-Rahurkar
Keyword(s):  
Quality Factor ◽  
Supply Voltage ◽  
Noise Analysis ◽  
Current Source ◽  
Cmos Technology ◽  
The Other ◽  
Active Inductor ◽  
Voltage Sensitivity ◽  
Current Mirror ◽  
Characterization Factors

A novel tuning principle for simple gyrator-based CMOS active inductor (AI) circuit is presented. The method makes use of Widlar current source to enhance the quality factor. The simulation of the proposed AI provides a maximum quality factor of 1819 at 2.88[Formula: see text]GHz. The AI shows the inductive bandwidth of 1.66[Formula: see text]GHz to 3.16[Formula: see text]GHz and power consumption of 6.87[Formula: see text]mW. The other characterization factors such as linearity, supply voltage sensitivity and noise analysis are discussed. The performance of the tunable AI using Widlar current source are compared with the same using a simple current mirror. An AI using a conventional current mirror (CCM) and Widlar current source have been implemented in the 0.18[Formula: see text][Formula: see text]m CMOS technology.

Sub-Volt Fully Balanced Differential Difference Amplifier

2014 ◽  
Vol 24 (01) ◽  
pp. 1550005 ◽  
Author(s):  
Fabian Khateb ◽  
Montree Kumngern ◽  
Spyridon Vlassis ◽  
Costas Psychalinos ◽  
Tomasz Kulej
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Floating Gate ◽  
Voltage Range ◽  
State Variable ◽  
Low Voltage Operation ◽  
Differential Difference Amplifier ◽  
Simulation Results ◽  
State Variable Filter

This paper presents a new CMOS structure for a fully balanced differential difference amplifier (FB-DDA) designed to operate from a sub-volt supply. This structure employs the bulk-driven quasi-floating-gate (BD-QFG) technique to achieve the capability of an ultra-low voltage operation and an extended input voltage range. The proposed BD-QFG FB-DDA is suitable for ultra-low-voltage low-power applications. The circuit is designed with a single supply of 0.5 V and consumes only 357 nW of power. The proposed circuit was simulated in a 0.18-μm TSMC CMOS technology and the simulation results prove its functionality and attractive parameters. An application example of a state variable filter is also presented to confirm the usefulness of the proposed BD-QFG FB-DDA.

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