A Bulk-Driven Quasi-Floating Gate Regulated Cascode Current Mirror and Its Application in Squarer Circuit

A regulated cascode current mirror (RGC) and its improved version with bulk driven quasi floating gate technique (BD-QFG) are presented in this paper. The proposed BD-QFG RGC current mirror (CM) is compared with the conventional (GD) RGC CM to show the performance improvement. The conventional and unconventional CM are implemented in Candace Virtuoso using 90 nm CMOS technology. For input current (Iin) varied from 0 to 200 μA and for 0.8 V supply voltage, the simulation results present that the proposed BD-QFG RGC CM has less variation in current transfer error (0.2%) as compared to the GD RGC CM (12%). The output voltage requirement for 200 µA input current is respectively 0.7 V and 0.17 V for the GD RGC CM and the BD-QFG RGC CM. The power consumption of the proposed circuit is 22.71 μW which is 0.15 μW higher than the GD RGC (22.56 μW). The total harmonic distortion (THD) of the proposed circuit is 0.4% which is 1.1% less than the conventional circuit (1.5%). All these improvements in the proposed BD-QFG RGC CM are attained at a cost of 0.05 GHz reduction in frequency (2.31 GHz). The minimum supply voltage of BD-QFG RGC CM and GD RGC CM is 0.4 V and

Design of Low Voltage Quasi-floating Self Cascode Current Mirror

In this paper, a modified structure of self-cascode structure is proposed. In the proposed structure, the MOSFET working in saturation mode is replaced by a Quasi-floating gate MOSFET by which the threshold voltage can be scaled, resulting in an increase in the drain-to-source voltage of other MOSFET operating in the linear region. The increased drain-to-source voltage results in a change in the operating region, which here is from linear to saturation regime. To exploit the performance of the proposed structure, the design of the current mirror circuit is shown in this paper. The proposed architecture when compared with its conventional design showed improvement in performance without affecting the other parameters. The complete design is done using MOSFET models of 180nm technology using Spice at supply dual supply of 0.5V.

A Potentiostat Readout Circuit with a Low-Noise and Mismatch-Tolerant Current Mirror Using Chopper Stabilization and Dynamic Element Matching for Electrochemical Sensors

This paper presents a potentiostat readout circuit with low-noise and mismatch-tolerant current mirror using chopper stabilization and dynamic element matching (DEM) for electrochemical sensors. Current-mode electrochemical sensors are widely used to detect the blood glucose and viruses in the diagnosis of various diseases such as diabetes, hyperlipidemia, and the H5N1 avian influenza virus (AIV). Low-noise and mismatch-tolerant characteristics are essential for sensing applications that require high reliability and high sensitivity. To achieve these characteristics, a proposed potentiostat readout circuit is implemented using the chopper stabilization scheme and the DEM technique. The proposed potentiostat readout circuit consists of a chopper-stabilized programmable gain transimpedance amplifier (TIA), gain-boosted cascode current mirror, and a control amplifier (CA). The chopper scheme, which is implemented in the TIA and CA, can reduce low frequency noise components, such as 1/f noise, and can obtain low-noise levels. The mismatch offsets of the cascode current mirror can be reduced by the DEM operation. The proposed current-mirror-based potentiostat readout circuit is designed using a standard 0.18 μm CMOS process and can measure the sensor current from 350 nA to 2.8 μA. The input-referred noise integrated from 0.1 Hz to 1 kHz is 21.7 pARMS, and the power consumption was 287.9 μW with a 1.8 V power supply.

A Charge Amplifier Based Complementary Metal–Oxide–Semiconductor Analog Front End for Piezoelectric Microphones in Hearing Aid Devices

In this paper, a low noise and low power analog front end for piezoelectric microphones used in hearing aid devices is presented. It consists of a Charge Amplifier, followed by a Variable Gain Amplifier and an Analog-to-Digital Converter. At the core of charge amplifier a two stage opamp with modified cascode current mirror is designed which achieves a gain of 93 dB and phase margin of 62°. Designed analog front end achieves an input referred noise of 0.12 μVrms and SNR of 74 dB. It consumes power of 430 μW from 1.8 V supply and occupies an area of 1.2 mm × 0.22 mm. Proposed circuit is designed and fabricated in 0.18 μm CMOS process. Designed circuit is interfaced with a sensor model of piezoelectric microphone, which mimics Ormia ochracea's auditory system, and its performance is successfully verified against simulation results.