scholarly journals An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

Electronics ◽  
2021 ◽  
Vol 10 (22) ◽  
pp. 2795
Author(s):  
B. Srinath ◽  
Rajesh Verma ◽  
Abdulwasa Bakr Barnawi ◽  
Ramkumar Raja ◽  
Mohammed Abdul Muqeet ◽  
...  
Keyword(s):  
Simulated Annealing ◽  
Integrated Circuits ◽  
Supply Voltage ◽  
Physical Design ◽  
Timing Constraints ◽  
Clock Distribution ◽  
Clock Skew ◽  
Tree Representation ◽  
Optimization Parameters ◽  
Simulation Results

Managing the timing constraints has become an important factor in the physical design of multiple supply voltage (MSV) integrated circuits (IC). Clock distribution and module scheduling are some of the conventional methods used to satisfy the timing constraints of a chip. In this paper, we propose a simulated annealing-based MSV floorplanning methodology for the design of ICs within the timing budget. Additionally, we propose a modified SKB tree representation for floorplanning the modules in the design. Our algorithm finds the optimal dimensions and position of the clocked modules in the design to reduce the wirelength and satisfy the timing constraints. The proposed algorithm is implemented in IWLS 2005 benchmark circuits and considers power, wirelength, and timing as the optimization parameters. Simulation results were obtained from the Cadence Innovus digital system taped-out at 45 nm. Our simulation results show that the proposed algorithm satisfies timing constraints through a 30.6% reduction in wirelength.

scholarly journals Module Based Floorplanning Methodology to Satisfy Voltage Island and Fixed Outline Constraints

Electronics ◽  
2018 ◽  
Vol 7 (11) ◽  
pp. 325 ◽  
Author(s):  
Srinath Balasubramanian ◽  
Arunapriya Panchanathan ◽  
Bharatiraja Chokkalingam ◽  
Sanjeevikumar Padmanaban ◽  
Zbigniew Leonowicz
Keyword(s):  
Integrated Circuits ◽  
Supply Voltage ◽  
State Of The Art ◽  
Power Reduction ◽  
Significant Rise ◽  
Tree Representation ◽  
Voltage Level ◽  
Island Constraints ◽  
Functional Blocks ◽  
Representation Scheme

Multiple supply voltage is the most prevalent method for low power reduction in the design of modern Integrated circuits. Floorplanning process in this design performs positioning of functional blocks in the layout satisfying both fixed outline and voltage island constraints. The floorplans while satisfying these two significant constraints causes significant rise in wirelength and congestion. In this paper, a congestion and wirelength aware floorplanning algorithm is proposed which allows effective placement of functional blocks in the layout to satisfying fixed outline and voltage island constraints simultaneously. To perform voltage island floorplanning, the proposed algorithm uses Skewed binary tree representation scheme to operate the functional blocks in its predefined voltage level. The proposed methodology determines the feasible dimensions of the functional blocks in the representation which aids the placement process for the reduction of congestion and wirelength. With these optimal dimensions of the functional blocks, floorplanning is also performed for the layouts of aspect 1:1, 2:1, and 3:1, to evaluate the ability of proposed algorithm for satisfying the fixed outline constraint. The proposed methodology is implemented in the layout of InternationalWorkshop on Logic and Synthesis (IWLS) benchmarks circuits for experimental purpose. The resulting floorplans were iteratively optimized for optimal reduction of wirelength and congestion. Experimental results show that the proposed methodology outperforms existing state-of-the-art approaches in wirelength reduction by about 18.65% and in congestion reduction by around 63%, while delivering the 30.35% power consumption.

Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits

2013 ◽  
Vol E96.C (4) ◽  
pp. 538-545
Author(s):  
Takeshi OKUMOTO ◽  
Kumpei YOSHIKAWA ◽  
Makoto NAGATA
Keyword(s):  
Integrated Circuits ◽  
Supply Voltage

scholarly journals Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 454
Author(s):  
You Wang ◽  
Yu Mao ◽  
Qizheng Ji ◽  
Ming Yang ◽  
Zhaonian Yang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Field Effect ◽  
Electrostatic Discharge ◽  
Field Effect Transistors ◽  
Test Method ◽  
Current Path ◽  
Simulation Results ◽  
Current Characteristics ◽  
Aided Design

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

Wear of a Tool in Double-Disk Lapping of Silicon Wafers

2010 ◽  
Author(s):  
Adam Barylski ◽  
Mariusz Deja
Keyword(s):  
Experimental Data ◽  
Integrated Circuits ◽  
Tool Wear ◽  
Silicon Wafers ◽  
Silicon Ingot ◽  
Proposed Model ◽  
Tool Wear Prediction ◽  
Simulation Results ◽  
High Degree ◽  
Kinematical Parameters

Silicon wafers are the most widely used substrates for fabricating integrated circuits. A sequence of processes is needed to turn a silicon ingot into silicon wafers. One of the processes is flattening by lapping or by grinding to achieve a high degree of flatness and parallelism of the wafer [1, 2, 3]. Lapping can effectively remove or reduce the waviness induced by preceding operations [2, 4]. The main aim of this paper is to compare the simulation results with lapping experimental data obtained from the Polish producer of silicon wafers, the company Cemat Silicon from Warsaw (www.cematsil.com). Proposed model is going to be implemented by this company for the tool wear prediction. Proposed model can be applied for lapping or grinding with single or double-disc lapping kinematics [5, 6, 7]. Geometrical and kinematical relations with the simulations are presented in the work. Generated results for given workpiece diameter and for different kinematical parameters are studied using models programmed in the Matlab environment.

Trajectory Optimization Applied to Space Rendezvous

2013 ◽  
Vol 756-759 ◽  
pp. 3466-3470
Author(s):  
Xu Min Song ◽  
Qi Lin
Keyword(s):  
Simulated Annealing ◽  
Optimization Model ◽  
Trajectory Optimization ◽  
Optimization Problem ◽  
Optimization Method ◽  
Nonlinear Constraints ◽  
Design Variables ◽  
Adaptive Simulated Annealing ◽  
Simulation Results

The trajcetory plan problem of spece reandezvous mission was studied in this paper using nolinear optimization method. The optimization model was built based on the Hills equations. And by analysis property of the design variables, a transform was put forward , which eliminated the equation and nonlinear constraints as well as decreaseing the problem dimensions. The optimization problem was solved using Adaptive Simulated Annealing (ASA) method, and the rendezvous trajectory was designed.The method was validated by simulation results.

scholarly journals AMPLIFIED NELDER-MEAD ALGORITHM FOR SOLVING OPTIMAL REACTIVE POWER PROBLEM

2018 ◽  
Vol 6 (11) ◽  
pp. 299-306
Author(s):  
K. Lenin
Keyword(s):  
Simulated Annealing ◽  
Power Loss ◽  
Reactive Power ◽  
Superior Performance ◽  
Real Power ◽  
Last Stage ◽  
Simulation Results ◽  
Power Problem ◽  
Nelder Mead Algorithm ◽  
Prime Solution

This paper presents Hybridization of Simulated Annealing with Nelder-Mead algorithm (SN) is proposed to solve optimal reactive power problem. The proposed Hybridized - Simulated Annealing, Nelder-Mead algorithm starts with a prime solution, which is produced arbitrarily and then the solution is disturbed into partitions. The vicinity zone is created, arbitrary numbers of partitions are selected and variables modernizing procedure is started in order to create a trail of neighbour solutions. This procedure helps the SN algorithm to explore the region around an existing iterate solution. The Nelder- Mead algorithm is used in the last stage in order to progress the most excellent solution found so far and hasten the convergence in the closing stage. The proposed Hybridization of Simulated Annealing with Nelder-Mead algorithm (SN) has been tested in standard IEEE 57,118 bus systems and simulation results show the superior performance of the proposed SN algorithm in reducing the real power loss and voltage profiles are within the limits.

Passive Components for RF-ICs

2012 ◽  
pp. 189-214
Author(s):  
Gianluca Cornetta ◽  
David J. Santos ◽  
José Manuel Vázquez
Keyword(s):  
Integrated Circuits ◽  
Quality Factor ◽  
Silicon Substrate ◽  
Supply Voltage ◽  
Magnetic Behavior ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Fully Integrated ◽  
Core Elements ◽  
Low Supply Voltage

The modern wireless communication industry is demanding transceivers with a high integration level operating in the gigahertz frequency range. This, in turn, has prompted intense research in the area of monolithic passive devices. Modern fabrication processes now provide the capability to integrate onto a silicon substrate inductors and capacitors, enabling a broad range of new applications. Inductors and capacitors are the core elements of many circuits, including low-noise amplifiers, power amplifiers, baluns, mixers, and oscillators, as well as fully-integrated matching networks. While the behavior and the modeling of integrated capacitors are well understood, the design of an integrated inductor is still a challenging task since its magnetic behavior is hard to predict accurately. As the operating frequency approaches the gigahertz range, device nonlinearities, coupling effects, and skin effect dominate, making difficult the design of critical parameters such as the self-resonant frequency, the quality factor, and self and mutual inductances. However, despite the parasitic effects and the low quality-factor, integrated inductors still allow for the implementation of integrated circuits with improved performances under low supply voltage. In this chapter, the authors review the technology behind monolithic capacitors and inductors on silicon substrate for high-frequency applications, with major emphasis on physical implementation and modeling.

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