scholarly journals 3.3V Transmitter Using 1.8V Transistors In A Cascode Configuration

2021 ◽  
Author(s):  
Marcs Ng
Keyword(s):  
Integrated Circuits ◽  
Transmission Rate ◽  
Carrier Injection ◽  
Digital Integrated Circuits ◽  
Negative Bias Temperature Instability ◽  
Hot Carrier ◽  
Bias Temperature Instability ◽  
Hot Carrier Injection ◽  
Capacitive Load ◽  
Ac Transmission

A voltage-mode transmitter using a 1.8V-to-3.3V levelshifter and cascoded output buffer is proposed. 1.8V TSMC 65nm transistors are used. The design is targeted to meet JEDEC Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits DC Specifications as well as an AC transmission rate of 200 MHz on a 30 cm 50Ω board trace terminated with a 4 pF capacitive load. Overstress voltages will not be exceeded in order to avoid device failure due to breaching Gate Oxide Integrity, Hot Carrier Injection, or Negative Bias Temperature Instability.

scholarly journals 3.3V Transmitter Using 1.8V Transistors In A Cascode Configuration

2021 ◽  
Author(s):  
Marcs Ng
Keyword(s):  
Integrated Circuits ◽  
Transmission Rate ◽  
Carrier Injection ◽  
Digital Integrated Circuits ◽  
Negative Bias Temperature Instability ◽  
Hot Carrier ◽  
Bias Temperature Instability ◽  
Hot Carrier Injection ◽  
Capacitive Load ◽  
Ac Transmission

A voltage-mode transmitter using a 1.8V-to-3.3V levelshifter and cascoded output buffer is proposed. 1.8V TSMC 65nm transistors are used. The design is targeted to meet JEDEC Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits DC Specifications as well as an AC transmission rate of 200 MHz on a 30 cm 50Ω board trace terminated with a 4 pF capacitive load. Overstress voltages will not be exceeded in order to avoid device failure due to breaching Gate Oxide Integrity, Hot Carrier Injection, or Negative Bias Temperature Instability.

scholarly journals Impact of process variations and long term degradation on 6T-SRAM cells

2007 ◽  
Vol 5 ◽  
pp. 321-325 ◽  
Author(s):  
Th. Fischer ◽  
A. Olbrich ◽  
G. Georgakos ◽  
B. Lemaitre ◽  
D. Schmitt-Landsiedel
Keyword(s):  
Supply Voltage ◽  
Process Variations ◽  
Deep Submicron ◽  
Carrier Injection ◽  
Negative Bias Temperature Instability ◽  
Electrical Fields ◽  
Hot Carrier ◽  
Bias Temperature Instability ◽  
Hot Carrier Injection

Abstract. In modern deep-submicron CMOS technologies voltage scaling can not keep up with the scaling of the dimensions of transistors. Therefore the electrical fields inside the transistors are not constant anymore, while scaling down the device area. The rising electrical fields bring up reliability problems, such as hot carrier injection. Also other long term degradation mechanisms like Negative Bias Temperature Instability (NBTI) come into the focus of circuit design. Along with process device parameter variations (threshold voltage, mobility), variations due to the degradation of devices form a big challenge for designers to build circuits that both yield high under the influence of process variations and remain functional with respect to long term device drift. In this work we present the influence of long term degradation and process variations on the performance of SRAM core-cells and parametric yield of SRAM arrays. For different use cases we show the performance degradation depending on temperature and supply voltage.

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