scholarly journals ISODATA SOPC-FPGA implementation of image segmentation using NIOS-II processor

Author(s):  
Radjah Fayçal ◽  
Ziet Lahcene ◽  
Benoudjit Nabil

<p>This paper presents an FPGA image segmentation-binarization system based on<em> </em>Iterative Self Organizing DATA <em>(ISODATA)</em> threshold using histogram analysis for embedded systems. The histogram module computes pixels levels statistics which are used by the ISODATA algorithm module to determine the segmentation threshold. In our case, this threshold binarizes a gray-scale image into two values 0 or 255. The prototype of the complete system uses an ALTERA CYCLONE-II DE2 kit with a lot of component and interfaces, such as the SD-CARD reader or a camera to read the image to be segmented, the FPGA which will implement the intellectual property (IP) core calculation with the NIOS processor, the VGA interface to view the results, and possibly of the ETHERNET interface for data transfer via internet. The use of FPGA contains the ISODATA, histogram, NIOS processor and others custom altera IPs hardware modules greatly improves processing speed and allows the binarization application to be embedded on a single chip. For the project elaboration, we have used QUARTUS-II software for the hardware development part with VHDL description, SOPC-builder or QSYS for the integration of NIOS-system, and NIOS-II-STB-ECLIPSE for the software program with eclipse c++ langage.</p><p> </p>

Author(s):  
Chan Boon Cheng ◽  
Asral Bahari Jambek

The implementation of a camera system with a field programmable gate array (FPGA) is an important step within research towards constructing a video processing architecture design based on FPGA. This paper presents the design and implementation of a camera system using the Nios II soft-core embedded processor from Altera. The proposed camera system is a flexible platform for the implementation of other systems such as image processing and video processing. The system architecture is designed using the Quartus II SOPC Builder System and implemented on an Altera DE2-70 development platform. The image or video is captured using a Terasic TRDB-D5M camera and stored into two different synchronous dynamic random access memories (SDRAM) using an SDRAM Controller. The specifications of the Terasic TRDB-D5M and SDRAM are examined to confirm that the recorded and stored data match. The results of this experiment show that the system is able to record and store data correctly into SDRAM. The data in the SDRAM correctly displays the recorded image on a VGA monitor.


Author(s):  
W. E. BLANZ ◽  
SHERI L. GISH

An image segmentation system which uses a connectionist classifier architecture as a central building block is described in this paper. The complete system, which consists of a feature extraction module and the connectionist classifier module, has been designed and implemented in digital VLSl; system architectural aspects as well as the procedure of adaptation of the system to different segmentation problems are discussed. The performance of the segmentation system on real world problems is demonstrated using scenes from industrial inspection, texture recognition, and combustion chamber research tasks.


2012 ◽  
Vol 433-440 ◽  
pp. 5659-5665
Author(s):  
Xian Hai Wang ◽  
Jin Ling Jia ◽  
Guang Jian Cheng ◽  
Hai Jun Zhang ◽  
Wen Jun Yu

This paper proposes a modularized method for the design and implementation of digital PID controller using DA algorithm based on Field Programmable Gate Array (FPGA) device. It is higher integration, lower power consumption, higher processing speed and more convenient reconfiguration compared with PID controllers based on software. The PID controller is modeled by using Simulink and DSP Builder to generate a system model. The controller coefficients are tuned conveniently by simulink and then pre-written into Look-up Tables(LUTs) in model of the proposed PID controller. After modeling, the simulation wave of step response for proposed PID controller is obtained easily by simulink. And the model of digital PID based on DA is then compiled by using Signal Compiler tool in DSP Builder provided by ALTERA corporation and synthesized by using QUARTUS II platform, and then the created file is downloaded into ALTERA’s FPGA device to implement the proposed PID controller.


2013 ◽  
Vol 712-715 ◽  
pp. 2733-2737
Author(s):  
Zhong An Yu ◽  
Chun Li Wang ◽  
Pei Yu Guo ◽  
Kong Kan

This system use PC as the core of image analysis and processing, with the single chip processor as the control core execution, combining with machine vision image processing technology, using advanced image processing algorithms, to achieve separation of the nut, and through experiments to test the correctness of the algorithm. The system has the advantage of a fast processing speed and high reliability. It not only save the manpower cost, but also improve the efficiency of the nut sorting.


2021 ◽  
Author(s):  
Cammillus S ◽  
Shanmugavel S

Abstract High-speed communication needs high data transfer capacity and low latency, which are the key parameters of high-speed communication. Converging different applications such as IPTV to high-speed networks requires high transmission capacity and low delay with good QoS. Delays related to IPTV are video buffering, synchronization, and switching delay that obstructs the client's excellent quality assistance. In an application like IPTV, the video signals are buffered (happened to be in near end routers), and they are recombined for the client when it is asserted. To achieve the above stated, memory banks are deployed in a set top box that is used to buffer the video signals that enter in, thereby reducing expected delay. Playback mechanism is also included along with the proposed model to accomplish a better outcome. Proposed RTL schematic design was simulated using Verilog, executed in Model Sim – Altera 10.1b (Quartus II 12.1 edition) and Cadence 5.


Author(s):  
Scott A. Miers ◽  
Glen L. Barna ◽  
Carl L. Anderson ◽  
Jason R. Blough ◽  
M. Koray Inal ◽  
...  

Wireless microwave telemetry addresses the difficult issue of obtaining transducer outputs from reciprocating and rotating components through the use of advanced electronic components. This eliminates the requirements of a direct link between the transducer and the acquisition system. Accuracy of the transducer signal is maintained through the use of a double frequency modulation (FM) technique which provides temperature stability and a 20 point calibration of each, complete system. Multiple transmitters can be used for larger applications and multiple antennas can be used to improve the signal strength and reduce the possibility of dropouts. Examples of piston temperature and automotive torque converter measurements are provided, showing the effectiveness of the wireless measuring technique.


1998 ◽  
Vol 08 (05n06) ◽  
pp. 637-659 ◽  
Author(s):  
GAIL ERTEN ◽  
FATHI M. SALAM

Two architectures for a programmable image processor with on-chip light sensing capability are described. The first is a VLSI implementation of a cellular neural network. The second is a distributed dual-structure mutation of the first architecture. The distributed dual architecture leverages the speed of silicon against the large silicon area requirements. Moreover, the innovative integrated nature of the dual-structure design significantly reduces the bottleneck and computational overload caused by data transfer from sensory focal plane to the image processor. The paper also describes VLSI chip prototypes and test results.


2016 ◽  
Vol 2016 ◽  
pp. 1-8
Author(s):  
Shaila Ghanti ◽  
G. M. Naik

Embedded systems are extensively used in home automation systems, small office systems, vehicle communication systems, and health service systems. The services provided by these systems are available on the Internet and these services need to be protected. Security features like IP filtering, UDP protection, or TCP protection need to be implemented depending on the specific application used by the device. Every device on the Internet must have network interface. This paper proposes the design of the embedded Secured Ethernet Interface System to protect the service available on the Internet against the SYN flood attack. In this experimental study, Secured Ethernet Interface System is customized to protect the web service against the SYN flood attack. Secured Ethernet Interface System is implemented on ALTERA Stratix IV FPGA as a system on chip and uses the modified SYN flood attack protection method. The experimental results using Secured Ethernet Interface System indicate increase in number of genuine clients getting service from the server, considerable improvement in the data transfer rate, and better response time during the SYN flood attack.


Author(s):  
Scott A. Miers ◽  
Glen L. Barna ◽  
Carl L. Anderson ◽  
Jason R. Blough ◽  
M. Koray Inal ◽  
...  

Wireless microwave telemetry addresses the difficult issue of obtaining transducer outputs from reciprocating and rotating components through the use of advanced electronic components. This eliminates the requirements of a direct link between the transducer and the acquisition system. Accuracy of the transducer signal is maintained through the use of a double frequency modulation technique which provides temperature stability and a 20 point calibration of the complete system. Multiple transmitters can be used for larger applications and multiple antennas can be used to improve the signal strength and reduce the possibility of dropouts. Examples of automotive torque converter and piston temperature measurements are provided, showing the effectiveness of the wireless measuring technique.


2019 ◽  
Vol 40 ◽  
pp. 218
Author(s):  
Lucas Alvarez Nogueira ◽  
Caison Rodrigues Ramos ◽  
Leonardo Carillo Bahia ◽  
Celso Becker Tischer

Actually, investors from several industrial sectors are looking for process improvements that aim at profitability and greater competitiveness in the market, however, characteristics such as cost, information and production agility are determining points for this. Open source input and output control platforms that integrate microcontrollers have been gaining ground in several sectors, where programmers have the ability to control processes and manage data. In this way, this article presents the development of a real time monitoring system of physical quantities based on Arduino and Raspberry. The complete system will consist of two modules, "Slave" and "Master", in which the data transfer of the measurements of temperature, humidity, luminosity, pressure and others will be carried out. The slave, formed by inexpensive sensors connected to an Arduino MEGA 2560, will be allocated at a remote location to acquire the desired physical quantities. The Master, will receive the information through an ethernet shield, connected in both modules, and will manage the database. The information stored on the web server can be accessed via internet browser, either in desktops or mobile systems through a friendly platform in real time. 


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