scholarly journals DIGITAL GENERATORS OF A PSEUDORANDOM PULSES SEQUENCE AND THEIR MODELING WITH USE OF FPGA INTHE ENVIRONMENT CAD QUARTUS II

2021 ◽  
Vol 5 (339) ◽  
pp. 83-90
Author(s):  
N.A. Seilova ◽  
D.Z. Dzhuruntaev ◽  
О.Zh. Mamyrbayev ◽  
A.B. Batyrgaliev ◽  
M. Turdalyuly
Keyword(s):  
Quartus Ii

CONVEYOR MODEL AND IMPLEMENTATION OF THE REAL NUMBERS ADDER ON FPGA

2020 ◽  
Vol 33 (109) ◽  
pp. 21-31
Author(s):  
І. Ya. Zeleneva ◽  
Т. V. Golub ◽  
T. S. Diachuk ◽  
А. Ye. Didenko
Keyword(s):  
Performance Improvement ◽  
Experimental Studies ◽  
Production Costs ◽  
Floating Point ◽  
Computing Device ◽  
Quartus Ii ◽  
Functional Blocks ◽  
Mental Testing ◽  
Processor Cores ◽  
Floating Point Numbers

The purpose of these studies is to develop an effective structure and internal functional blocks of a digital computing device – an adder, that performs addition and subtraction operations on floating- point numbers presented in IEEE Std 754TM-2008 format. To improve the characteristics of the adder, the circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This allows you to perform addition / subtraction operations on several numbers at the same time, which increas- es the performance of calculations, and also makes the adder suitable for use in modern synchronous cir- cuits. Each block of the conveyor structure of the adder on FPGA is synthesized as a separate project of a digital functional unit, and thus, the overall task is divided into separate subtasks, which facilitates experi- mental testing and phased debugging of the entire device. Experimental studies were performed using EDA Quartus II. The developed circuit was modeled on FPGAs of the Stratix III and Cyclone III family. An ana- logue of the developed circuit was a functionally similar device from Altera. A comparative analysis is made and reasoned conclusions are drawn that the performance improvement is achieved due to the conveyor structure of the adder. Implementation of arithmetic over the floating-point numbers on programmable logic integrated cir- cuits, in particular on FPGA, has such advantages as flexibility of use and low production costs, and also provides the opportunity to solve problems for which there are no ready-made solutions in the form of stand- ard devices presented on the market. The developed adder has a wide scope, since most modern computing devices need to process floating-point numbers. The proposed conveyor model of the adder is quite simple to implement on the FPGA and can be an alternative to using built-in multipliers and processor cores in cases where the complex functionality of these devices is redundant for a specific task.

Research and Design of Digital Clock Based on FPGA

2011 ◽  
Vol 187 ◽  
pp. 741-745 ◽  
Author(s):  
Juan Hua Zhu ◽  
Ang Wu ◽  
Juan Fang Zhu
Keyword(s):  
Design Method ◽  
Display Time ◽  
Development Environment ◽  
Display Module ◽  
Digital Clock ◽  
Clock System ◽  
Quartus Ii ◽  
Hardware Description ◽  
Fpga Chip ◽  
Led Lights

A digital clock system designed by using VHDL hardware description language is presented in this paper. The proposed architecture fully utilizes the digital clock system available on FPGA chips based top-down design method in the Quartus II development environment. The Clock system is divided into four design modules: core module, frequency_division module, display module and tune module. It not only can time accurately and display time, but also can reset and adjust time. The LED lights will flash and the loudspeaker will tell time on the hour. The architecture is implemented and verified experimentally on a FPGA board. Because of the universality of digital clock and the portability of VHDL language, it can be applied directly in various designs based on FPGA chip.

Improving Performance of a Multi-Bit Arithmetic Logic Unit

2021 ◽  
Vol 26 (1) ◽  
pp. 40-53
Author(s):  
A.N. Yakunin ◽  
◽  
Aung Myo San ◽  
Khant Win ◽  
◽  
...  
Keyword(s):  
High Speed ◽  
Operating Time ◽  
Arithmetic Logic Unit ◽  
Maximum Delay ◽  
Sequential Organization ◽  
Quartus Ii ◽  
Logic Unit

In modern microprocessors to reduce the time resources the arithmetic-logic units (ALU) with an increased organization of arithmetic carry, characterized by high speed, compared to ALU with sequential organization of the arithmetic carry, are commonly used. However, while increasing the bit number of the input operands, the operating time of ALU of ALU with the accelerated arithmetic carry increases linearly depending on the number of bits. Therefore, the development of ALU, providing higher performance than the existing known solutions, is an actual task. In this work the analysis of ALU with sequential and accelerated organization of the arithmetic carry has been performed. To increase the speed of the operation, a multi-bit ALU has been developed. The simulation of ALU circuits has been executed in Altera Quartus –II CAD environment. The comparison has been performed by the number of logical elements and the maximum delay as a result of modeling the ALU circuits for 4, 8, 16, 32, and 64 bits. A scheme for checking the results has been implemented to confirm the reliability of developed ALU. As a result, it has been found that when performing operations with the 64-bit operands, the developed ALU reduces the maximum delay by 53 % compared to ALU with sequential arithmetic carry and by 35.5 % compared to ALU with the accelerated arithmetic carry, respectively.

scholarly journals Design and Implementation of LCG-Trivium Key Stream Generator into FPGA

2018 ◽  
Vol 7 (3) ◽  
pp. 186
Author(s):  
Tchahou Tchendjeu A. E ◽  
Tchitnga Robert ◽  
Fotsin Hilaire B
Keyword(s):  
Stream Cipher ◽  
Clock Cycle ◽  
State Machine ◽  
Initial Value ◽  
Design And Implementation ◽  
Generator Circuit ◽  
Quartus Ii ◽  
Initialization Vector ◽  
Linear Congruential Generator ◽  
Linear Congruential

<p>This paper presents the Design and implementation into Field ProgrammableGate Array (FPGA) of a combine stream cipher and a simple linear congruential generator circuit to produce key stream. The LCG circuit is used to produce initialization vector (IV) each 2<sup>64</sup> clock cycle to the cipher trivium in other to strengthen the complexity of the cipher to known attacks on trivium. The LCGTrivium is designed to generate 2<sup>144</sup> bits of keystream from an 80-bits secret and a variable 80-bits initial value. To implement the LCG-Trivium on FPGA, we use VHDL to build a simple LCG and Trivium and a state machine to synchronize the functioning of the LCG and Trivium. The number of gates, memory and speed requirement on FPGA is giving after analysis. The design is simulated, synthesized and implemented in Quartus II 10.1, ModelSim-Altera 6.5 and Cyclone IV E EP4CE115F29C7N.</p>

scholarly journals High Performance Energy Efficient Computation Elements of Processing Unit

2019 ◽  
Vol 9 (2) ◽  
pp. 2450-2455
Keyword(s):  
Energy Efficient ◽  
High Performance ◽  
Logic Gate ◽  
Processing Unit ◽  
Efficient Computation ◽  
Quartus Ii ◽  
Efficient Processing ◽  
Exclusive Or ◽  
Design Logic

in our manuscript, various circuits for arithmetic summation are compared. Cadence 90nm technology and Quartus II EP2C20F484C7 are used for implementation of design. Logic gate-based adders, PFCA, TG and HSD technique-based adders characteristics are analyzed. Y finding is PFCA with 10T transistor performs slightly efficient compare to its counterpart. Exclusive OR-NOR design is optimum for least delay Adders for high performance energy efficient processing unit.

scholarly journals Implementation of a camera system using nios II on the altera DE2-70 board

2019 ◽  
Vol 14 (2) ◽  
pp. 513
Author(s):  
Chan Boon Cheng ◽  
Asral Bahari Jambek
Keyword(s):  
Video Processing ◽  
Random Access ◽  
Camera System ◽  
Embedded Processor ◽  
Nios Ii ◽  
Development Platform ◽  
Quartus Ii ◽  
Field Programmable ◽  
Sdram Controller ◽  
Recorded Image

The implementation of a camera system with a field programmable gate array (FPGA) is an important step within research towards constructing a video processing architecture design based on FPGA. This paper presents the design and implementation of a camera system using the Nios II soft-core embedded processor from Altera. The proposed camera system is a flexible platform for the implementation of other systems such as image processing and video processing. The system architecture is designed using the Quartus II SOPC Builder System and implemented on an Altera DE2-70 development platform. The image or video is captured using a Terasic TRDB-D5M camera and stored into two different synchronous dynamic random access memories (SDRAM) using an SDRAM Controller. The specifications of the Terasic TRDB-D5M and SDRAM are examined to confirm that the recorded and stored data match. The results of this experiment show that the system is able to record and store data correctly into SDRAM. The data in the SDRAM correctly displays the recorded image on a VGA monitor.

Implementation of CRC in 10-Gigabit Ethernet Based on FPGA

2014 ◽  
Vol 599-601 ◽  
pp. 1548-1552
Author(s):  
Bin Li ◽  
Zhi Ping Huang ◽  
Shao Jing Su ◽  
Jun Peng Hu
Keyword(s):  
Traditional Method ◽  
Environmental Constraints ◽  
Data Input ◽  
Gigabit Ethernet ◽  
Parallel Data ◽  
Quartus Ii ◽  
Parallel Input ◽  
10 Gigabit Ethernet

This paper describes the algorithm principle of CRC-32 codes, and then proposes multiple bits parallel input to achieve CRC-32 checksum on the basis of the principle. To design modules using VHDL language in Quartus II environment based on Altera’s EP4SGX230KF40C2 chip. Compared to traditional method of serial and 8 bits parallel data input, implementation of the program integrates 16, 32 and 64 bits parallel data input modes, the user can select the appropriate modules according to their needs and environmental constraints, which will greatly enhance the ability to adapt to the system and meet the needs of a variety of environments.

Design and Implementation of Intelligent Digital Photo Frame Based on FPGA

2013 ◽  
Vol 380-384 ◽  
pp. 3296-3299
Author(s):  
Dan Dan Han ◽  
Tian Chi Zhang ◽  
Jing Zhang
Keyword(s):  
System Optimization ◽  
Software System ◽  
Digital Photo ◽  
Design And Implementation ◽  
Traditional Design ◽  
Quartus Ii ◽  
Functional Correctness ◽  
Integrate Design ◽  
High Degree ◽  
Observation Results

SOPC technology of Nios II is Used for the design of intelligent digital photo frame in this paper. Developers can integrate design according to actual needs, fundamentally changing the lack of traditional design. Digital photo frame as a whole project is divided into two parts of the hardware module and software system. Functional correctness is verified by Quartus II, further downloaded to the FPGA for debugging, the observation results showed that digital photo frame has a high degree of freedom in the system optimization, which can be extended the life of the product on the market, greatly improving the performance of multi-function digital photo frame.

Sign in / Sign up

Export Citation Format

Share Document