Reducing Buffering Delay Using Memory Arbitration Mechanism for IPTV Based Applications

High-speed communication needs high data transfer capacity and low latency, which are the key parameters of high-speed communication. Converging different applications such as IPTV to high-speed networks requires high transmission capacity and low delay with good QoS. Delays related to IPTV are video buffering, synchronization, and switching delay that obstructs the client's excellent quality assistance. In an application like IPTV, the video signals are buffered (happened to be in near end routers), and they are recombined for the client when it is asserted. To achieve the above stated, memory banks are deployed in a set top box that is used to buffer the video signals that enter in, thereby reducing expected delay. Playback mechanism is also included along with the proposed model to accomplish a better outcome. Proposed RTL schematic design was simulated using Verilog, executed in Model Sim – Altera 10.1b (Quartus II 12.1 edition) and Cadence 5.

Design and implementation of OLT switching function in 40/10G TDM-PON experimental system

The access network is developing towards large capacity, wide-coverage, and low delay, which puts forward higher requirements for network structure and data exchange performance of optical access network equipment. In this paper, we have designed a high-speed optical network device with 40/10G TDM-PON. To effectively solve the problem of network switching capability in high-speed data transmission, we propose a low delay large capacity switching algorithm, which minimizes the network switching delay. We model the network by integer linear programming and simulate the network based on OMNeT++. The simulation results show that the algorithm can effectively solve the problem of network switching delay in the high-speed network environment.

Synthesis of Low-Voltage Logic Gates on Surrounding Gate SOI CMOS Nanotransistors

We discuss the issues of synthesis of low-voltage logic gates on cylindrical surrounding gate SOI CMOS nanotransistors in the supply voltage range up to 0.8 V. In this transistor architecture, it becomes possible to more effectively control the charge in its working area, primarily due to its design parameters. It is also characterized by effective suppression of short-channel effects and a low capacitance value. This leads to a decrease in the level of power dissipation in combination with a reduction in the occupied area. TCAD models of n- and p-types nanotransistors have been developed. The anomalous behavior of the dependence of the threshold voltage on the diameter of the working area is revealed, which is associated with the peculiarities of the manifestation of short-channel effects due to the capacitive interaction of the gate-channel regions and drain-source transitions at small gate lengths. They were used to select prototypes of transistors with optimal parameters for the synthesis of complex logic gates with low supply voltage. Using the mathematical core of the HSPICE program, the dynamic characteristics of the developed physical models of the inverter, the inverter chain, and the XOR2 are numerically investigated. At control voltages of 0.8 V and a frequency of 50 GHz, the inverter model predicts a maximum switching delay of 3.3 ps, a limit level of active power of 1.1 mkW, static 0.3 pW, the XOR2 predicts a maximum switching delay of 8.6 ps, a limit level of active power of 4.9 mkW, static 1.5 pW. The minimum of the product "delay * power" of the adder is at a supply voltage of 0.72 V. Its position does not depend on the set of input signals. At the same time, the maximum switching delay is 10.8 ps, the maximum active power level is 3.9 mkW. The totality of the obtained characteristics allows us to consider the analyzed transistor architecture for creating low-power electronic devices.

Correction to: Conversion of geared DC motor into stepper motor using switching delay time signals

A correction to this paper has been published: https://doi.org/10.1007/s42452-021-04542-3

Low-Cost Active Anomaly Detection with Switching Latency

Consider the problem of detecting anomalies among multiple stochastic processes. Each anomaly incurs a cost per unit time until it is identified. Due to the resource constraints, the decision-maker can select one process to probe and obtain a noisy observation. Each observation and switching across processes accompany a certain time delay. Our objective is to find a sequential inference strategy that minimizes the expected cumulative cost incurred by all the anomalies during the entire detection procedure under the error constraints. We develop a deterministic policy to solve the problem within the framework of the active hypothesis testing model. We prove that the proposed algorithm is asymptotic optimal in terms of minimizing the expected cumulative costs when the ratio of the single-switching delay to the single-observation delay is much smaller than the declaration threshold and is order-optimal when the ratio is comparable to the threshold. Not only is the proposed policy optimal in the asymptotic regime, but numerical simulations also demonstrate its excellent performance in the finite regime.

Conversion of geared DC motor into stepper motor using switching delay time signals

In solar tracking system, general stepper motor is used to control the stepwise movement and low speed of solar panel in vertical motion. Degree of rotation is directly proportional to stepwise movement (stepping method) of stepper motor. But it is cumbersome process to hold a solar panel at a particular vertical position depending on the sun’s position using low cost stepper motors. So, geared DC motor is implemented into stepper motor for low-speed applications using Stepping Method (GDCSM). Degree per step movement of geared DC motor is identified using Step angle switching delay time signal (A) of microcontroller. Speed of geared DC motor is controlled by passing fixed time interval between the pulses where the pulses have fixed width. Controlling speed is implemented by using Step delay time signal (D) of microcontroller. Combining effect of switching delay time signals A and D represents the Stepping Method. Stepping method resembles the step movement and controlling speed of the stepper motor. Speed of 10RPM & 30RPM geared DC motors is operated at 10V DC power supply. Microcontroller ATmega 328P with switching delay time signals is used to control the geared DC motors. Performance of 10RPM & 30RPM GDCSM is analyzed with stepper motors in terms of Relative slip degree error per revolution (RE$$_\mathrm{{S}}$$ S ) and acceptable slippage degree tolerance under open loop condition. Change in consuming voltage tolerance ($$\varDelta$$ Δ ) during rotation of GDCSM is another parameter which is used to maintain the constant actual total step count per revolutions of GDCSM. At 40 ms of step angle delay time (A), 10RPMGDCSM has 120 steps per revolution. At 25 ms of A, 30RPMGDCSM has 55 steps per revolution. Speed of 10RPM & 30RPM GDCSM is controllable up to 2RPM when its RE$$_\mathrm{{S}}$$ S or acceptable slippage degree tolerance value is less than or equal to 1%. If $$\varDelta$$ Δ value of GDCSM is less than or equal to − 0.4%, then it behaves like stepper motor. GDCSM is suitable to hold and control vertical position of solar tracking system with low speed and step movement. Performance of geared DC motor experimentally showed better result than commercial available stepper motors like 28BYJ-48 or STP-43d1027-01.

Development of a Printed E-Textile for the Measurement of Muscle Activation via EMG for the Purpose of Gesture Control

This paper details the development of an e-textile gesture controller using screen-printed electrodes to measure Electromyography (EMG); the electrical signals produced in a muscle during its use. The final e-textile consists of 7 fabric electrodes able to take measurements from three muscular groups in the right forearm. When accompanied with processing circuitry, also produced in this study, a total of five gestures are uniquely identified with an average accuracy of ~93% when operating with a switching delay of 150 ms or greater.