scholarly journals Development of Information-Control Interface for Communication of Spacecraft Units

2020 ◽  
Vol 23 (2) ◽  
pp. 91
Author(s):  
M. N. Yankovoy ◽  
L. V. Markaryan
Keyword(s):  
Information Control ◽  
Verilog Hdl ◽  
Control Interface ◽  
Quartus Ii

Представлена разработка протокола простой и надежной передачи данных для блока управления антенной в жестких условиях эксплуатации. Логический уровень протокола реализован на ПЛИС на базе протокола HDLC. Физическая линия передачи данных представляет резервированный, гальваноразвязанный интерфейс с биполярным самосинхронизирующимся кодом Manchester-II.Актуальность разработки протокола обусловлена внедрением отечественной элементной базы, устойчивой к жестким воздействиям окружающей среды, в том числе и радиации, и степенью важности развития космической отрасли в целом, а также сфер, зависящих от нее.Рассмотрено назначение блока управления антенной. Обоснована необходимость разработки протокола информационно-управляющего сопряжения для блока управления. Проведен обзор научно-технической информации о составляющих данного протокола. Рассмотрены физический, канальный и информационный уровни разработанного протокола, а также представлена реализация канального и информационного уровня на языке Verilog HDL для ПЛИС.В программе Quartus-II разработан программный код, который реализует канальный и информационный уровни передачи данных на основе протокола информационно-управляющего сопряжения блока управления антенной с блоком-вычислителем. После чего из отдельных блоков кода формируется схемотехнический проект, где для блоков задаются входные и выходные сигналы.Моделирование протокола передачи данных проведено в среде для отладки ModelSim-Altera, а также на отработочной плате. Моделирование подтвердило правильность выбранных решений в процессе создания протокола передачи данных. На заданную команду получена верная ответная квитанция с двумя байтами контрольной суммы. Переданные данные равны принятым данным, и контрольная сумма при приеме и передаче равны друг другу.Материал, представленный в данной научной статье, может быть принят разработчиками за основу реализации обмена данными между техническими устройствами, для которых остро стоит вопрос экономии ресурсов ПЛИС.

Research and Design of Asynchronous FIFO Based on FPGA

2014 ◽  
Vol 644-650 ◽  
pp. 3440-3444
Author(s):  
Bing Qi Liu ◽  
Ming Zhe Liu ◽  
Gang Yang ◽  
Xiao Bo Mao ◽  
Huai Liang Li
Keyword(s):  
Design Method ◽  
Stable State ◽  
Gray Code ◽  
Validity And Reliability ◽  
Verilog Hdl ◽  
Simulation Test ◽  
Development Platform ◽  
Module Design ◽  
Quartus Ii ◽  
Research And Design

In this article, a design method of asynchronous FIFO memory based on FPGA is put forward. With FPGA as the core controller, We adopt Verilog HDL and top-down design method to build a top-level module design and also analyze the mark logic of asynchronous FIFO and the elimination of semi-stable state under Quartus II development platform. Besides, with the application of Gray code conversion technology, not only the reliable transmission of data is guaranteed but also design efficiency is improved. Through contrast experiment analysis and simulation test, the validity and reliability of asynchronous FIFO memory are verified, meeting the basic requirement that FIFO can hold more enough data without spillovers despite the fullness of data.

Field Programmable Gate Array (FPGA) Based Microwave Oven

2019 ◽  
Vol 892 ◽  
pp. 120-126
Author(s):  
Thangavel Bhuvaneswari ◽  
Nor Hidayati Abdul Aziz ◽  
Jakir Hossen ◽  
Chinthakunta Venkataseshaiah
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
Controller Design ◽  
Microwave Oven ◽  
High Potential ◽  
Verilog Hdl ◽  
Quartus Ii ◽  
Field Programmable ◽  
Real Time Applications ◽  
Simulation Results

In this paper, an FPGA-based microwave oven controller design which can be implemented using Altera DE1 development board is presented. The motivation for this work is to explore FPGA for real time applications. First, a microwave oven controller design architecture that could fit into Altera DE1 board, utilizing on-board peripherals is developed. Then, using the proposed architecture, the design is implemented using Verilog HDL. The microwave oven functionalities are demonstrated using Altera DE1 development board by means of Quartus II 13.0 software. The testbenches are created and waveforms are generated using Modelsim 10.1d software. The simulation results for various cases have been presented and the results confirmed that all the basic functionalities of a practical microwave oven can be realized. The proposed FPGA based controller has a high potential for incorporation in microwave ovens.

Design and Implementation of Floyd-Steinberg Algorithm Based on FPGA

2015 ◽  
Vol 738-739 ◽  
pp. 350-353
Author(s):  
Jun Yang ◽  
Zong Jing Li ◽  
Wen Long Li
Keyword(s):  
Real Time ◽  
High Speed ◽  
Complex Multiplication ◽  
Error Diffusion ◽  
Computation Complexity ◽  
Time Error ◽  
Verilog Hdl ◽  
Memory Space ◽  
Design And Implementation ◽  
Quartus Ii

In this paper, we put forward an innovation method of high-speed and real-time error diffusion, which is based on Floyd-Steinberg algorithm. The design introduces LUT(look up table) and pipeline technology instead of complex multiplication operations, which accesses to the memory frequently. The whole design uses Verilog HDL language to program and Quartus ii 8.0 to synthesize and layout. At the end of the paper, we use a 48 pixel as an example, then simulate and verify it on the Modesim, which can prove the correctness of the design. Compared with the standard Floyed-Steinberg algorithm, this design can reduce the computation complexity, use a smaller memory space to exchange lots of logic units and increase the throughput of the algorithm. Besides, it has the advantages of good reconfigurability, simple hardware structure and high real-time.

Research and Design of Beamforming Device of SLC-LSCMA Algorithm Based on FPGA

2013 ◽  
Vol 347-350 ◽  
pp. 1677-1681
Author(s):  
Qing Fang Zhou ◽  
Yan Yan Yu ◽  
Lei Wang ◽  
Jun Yang
Keyword(s):  
Least Squares ◽  
Satellite Communications ◽  
Clock Frequency ◽  
Verilog Hdl ◽  
Description Language ◽  
Quartus Ii ◽  
Hardware Description ◽  
Timing Simulation ◽  
Array Beamforming ◽  
Research And Design

In this paper,we design a uniform circular array beamforming device of 16 yuan based on the least squares SLC-LSCMA algorithm (based on the linear subspace constrained least squares cma) high stability and rapid convergence for the foundation. The design of the complete beam-forming the SLC-LSCMA algorithm by plural, time-multiplier and accumulators, which uses less resources and faster than the traditional algorithm. The beamforming device uses hardware description language of Verilog HDL , and wires on the QUARTUS II 8.0. Finally the beamforming device is downloaded to the Alteras EP2C35F672C6, and its timing simulation can be run properly in the 50MHz clock frequency. This design can be widely used in mobile communication and satellite communications.

Design of the Digital Phase Meter with GPIB Interface Based on FPGA

2012 ◽  
Vol 490-495 ◽  
pp. 243-247
Author(s):  
Hong He ◽  
Ya Nan Qi ◽  
Zhi Hong Zhang ◽  
Bao Sheng Yu
Keyword(s):  
Transmission Rate ◽  
Lower Price ◽  
Simple Circuit ◽  
Verilog Hdl ◽  
Digital Phase ◽  
Quartus Ii ◽  
Design Cycle ◽  
Gpib Interface

Comparing with the traditional phase meter, the design of digital phase meter with GPIB interface based on FPGA have some advantages, such as the high date transmission rate, the simple circuit, short design cycle and the lower price. The principle of this design meets with the standard of IEEE488.2 and use Verilog HDL language to design every interface. Then compile simulate it in Quartus II. Finally download it to the FPGA experiment board to realize every function. It makes the date transmission more stable and reliable through the design of GPIB interface

scholarly journals A New Technology for Reducing Power Consumption in Synchronous Digital Design Using Tri-State Buffer

2018 ◽  
Vol 11 (2) ◽  
pp. 60-66
Author(s):  
Hussein Shakor Moghee
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
New Technology ◽  
Reducing Power ◽  
Digital Design ◽  
Total Power ◽  
Verilog Hdl ◽  
Design And Implementation ◽  
Quartus Ii ◽  
State Technique

This research paper deals with design and implementation of low power 8-bit arithmetic logic units. The main part of power consumption is consumed in ALU in any processor. Therefore, reducing power dissipation in ALU should be requiring. The proposed technique disabled one of the main block of ALU using tri-state logic which is not necessary to use, except the required processes. In this work, the suggested design is realized by using ASIC methodologies. In order to implement the arithmetic and logic architectures, 130 nm standard cell libraries are used for ASIC execution. The architecture of the design has been created using Verilog HDL language. In addition, it is simulated using ModelSim-Altera 10.3c (Quartus II 14.1) tools. By using tri-state technique, dynamic power and total power are decreased

scholarly journals Study of Data Security Algorithms using Verilog HDL

2015 ◽  
Vol 5 (5) ◽  
pp. 1092
Author(s):  
M. Sumathi ◽  
D. Nirmala ◽  
R. Immanuel Rajkumar
Keyword(s):  
Performance Evaluation ◽  
Data Security ◽  
Hardware Description Language ◽  
Performance Study ◽  
Verilog Hdl ◽  
Description Language ◽  
Quartus Ii ◽  
Encryption And Decryption ◽  
Different Types ◽  
Hardware Description

This paper describes an overview of data security algorithms and its performance evaluation. AES, RC5 and SHA algorithms have been taken under this study. Three different types of security algorithms used to analyze the performance study. The designs were implemented in Quartus-II software. The results obtained for encryption and decryption procedures show a significant improvement on the performance of the three algorithms. In this paper, 128-bit AES, 64-bit of RC5 and 512-bit of SHA256 encryption and Decryption has been made using Verilog Hardware Description Language and simulated using ModelSim.

FPGA Implementation of Direct Digital Frequency Synthesizer

2013 ◽  
Vol 380-384 ◽  
pp. 3312-3315
Author(s):  
Hui Jing Yang ◽  
Fan Yu
Keyword(s):  
Frequency Synthesizer ◽  
Design Parameters ◽  
Input Output ◽  
Verilog Hdl ◽  
Digital Frequency ◽  
Quartus Ii ◽  
Direct Digital Frequency Synthesizer ◽  
Simulation Results ◽  
Phase Amplitude ◽  
Frequency Phase

Direct digital frequency synthesizer (referred to as DDS) is a kind of complete digital frequency synthesizer. In this article the principle of DDS were introduced. Set the design index of distortion and resolution, and design parameters of DDS in accordance with the index. DDS design describes by Verilog HDL, implement controlling four parameters of the waveform, frequency, phase, amplitude. Using FPGA and Quartus II/Nios IIwhich is Altera EDA software, realize DDS and its peripheral input / output and DA platform. The final direct to DDS simulation results and the overall DDS platform oscilloscope experimental data, verify the correctness of the design of DDS with the two data.

Design and Implementation of Signal Generator Based on DDS

2013 ◽  
Vol 380-384 ◽  
pp. 3643-3647
Author(s):  
Hong He ◽  
Jin Zhou Zhang ◽  
Zhi Hong Zhang
Keyword(s):  
Duty Cycle ◽  
Pulse Width ◽  
Signal Generator ◽  
Direct Digital Synthesis ◽  
Verilog Hdl ◽  
Design And Implementation ◽  
Quartus Ii ◽  
Digital Synthesis ◽  
Frequency Phase

A signal generator with adjustable frequency, phase and duty cycle is designed in this paper. The design of this signal generator is based on the technology of direct digital synthesis (DDS).The classic structure of DDS is presented and its principles are introduced in detail. The key modules of the design such as phase accumulator and pulse width processing are implemented by verilog HDL language. With suitable FPGA, the designed signal generator and all modules of the design are simulated successfully in Quartus II.

The Research and Design of 915MHz Radio Frequency Reader Based on FPGA

2012 ◽  
Vol 462 ◽  
pp. 524-531
Author(s):  
Shi Lin Fang
Keyword(s):  
Radio Frequency ◽  
Digital Signal ◽  
Flexible Structure ◽  
Type B ◽  
Verilog Hdl ◽  
Rfid Reader ◽  
Quartus Ii ◽  
Cmos Chip ◽  
And Function ◽  
Research And Design

Based on ISO/IEC 18000-6 Type B protocol, 915MHz RFID reader has been designed. FPGA is used to process the digital signal that is based on the protocol and C8051F020 is used as the controller. Each module in FPGA and verification module is designed by Verilog HDL. They are synthesized by Quartus II with EP1C6Q240C8 CMOS chip of the Altera as the target device, and they are verified on both timing and function. The result shows that it could satisfy the technology index of ISO/IEC18000-6 Type B requests and possess the advantages of flexible structure, small size and easily upgrading, etc.

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