SiC Lateral Diodes for ESD Protection of High Temperature Integrated Circuits

Lateral diode based electrostatic discharge (ESD) protection for silicon-on-insulator (SOI) circuits suffer from high leakage currents at elevated temperatures. This may degrade the performance of SOI based integrated circuits and can also limit the life of the system. Wide bandgap materials such as silicon carbide (SiC) can potentially mitigate this problem because of their low intrinsic carrier concentrations. In this study, lateral SiC diodes have been fabricated and evaluated at high temperatures for ESD protection. The leakage level of SiC lateral diodes with an active area of 700 μm2 is shown to be as low as 1 pA at 200 °C and 25 pA at 300 °C. Furthermore, based on circuit simulations, the number of lateral SiC diodes required to protect against an ESD event (human body model) at 2kV was determined to be 20 devices. Under reverse bias conditions (at 20V), these diodes would have a total leakage current of 20 pA at room temperature and 500 pA at 300 °C. .

A study on the importance of isolation of the active regions for high performance organic circuits

ABSTRACTThe authors present electrical comparisons on an array of test structures including organic lateral diodes and thin film transistors (OTFT), fabricated with a range of disordered and polycrystalline organic semiconductors, to examine the increasing need for effective isolation for organic-based circuits. As the minimum feature size decreases, circuit components become closely positioned, which leads to increased electrical crosstalk. The organic semiconductors utilised for this work include solution-processable organic semiconductors such as disordered polymers P3HT and PTAA, and a polycrystalline material TIPS-pentacene. In order to predict the magnitude required for isolation for the different semiconductors, simple test structures have been designed consisting of two gold electrodes separated by a distance ranging from 4 μm up to 2000 μm. The bulk conductivity from such test structures provides the limits at which circuit components may be placed for crosstalk free operation. The work presented culminates in the development of an isolation layer to help reduce the off-currents and gate leakages of the OTFTs.