First-principles investigation of copper diffusion barrier performance in defective 2D layered materials

This paper investigates the diffusion barrier performance of 2D layered materials with pre-existing vacancy defects using first-principles density functional theory. Vacancy defects in 2D materials may give rise to a large amount of Cu accumulation, and consequently, the defect becomes a diffusion path for Cu. Five 2D layered structures are investigated as diffusion barriers for Cu, i.e., graphene with C vacancy, hBN with B/N vacancy, and MoS2 with Mo/2S vacancy. The calculated energy barriers using climbing image - nudged elastic band show that MoS2-V2S has the highest diffusion energy barrier among other 2D layers, followed by hBN-VN and graphene. The obtained energy barrier of Cu on defected layer is found to be proportional to the length of the diffusion path. Moreover, the diffusion of Cu through vacancy defects is found to modulate the electronic structures and magnetic properties of the 2D layer. The charge density difference shows that there exists a considerable charge transfer between Cu and barrier layer as quantified by Bader charge. Given the current need for an ultra-thin diffusion barrier layer, the obtained results contribute to the field of application of 2D materials as Cu diffusion barrier in the presence of mono-vacancy defects.

Integration technologies for chips with 2D materials

With compact footprint, low energy consumption, high scalability, and mass producibility, chip-scale integrated devices are an indispensable part of modern technological change and development. Recent advances in two-dimensional (2D) layered materials with their unique structures and distinctive properties have motivated their on-chip integration, yielding a variety of functional devices with superior performance and new features. To realize integrated devices incorporating 2D materials, it requires a diverse range of device fabrication techniques, which are of fundamental importance to achieve good performance and high reproducibility. This paper reviews the state-of-art fabrication techniques for the on-chip integration of 2D materials. First, an overview of the material properties and on-chip applications of 2D materials is provided. Second, different approaches used for integrating 2D materials on chips are comprehensively reviewed, which are categorized into material synthesis, on-chip transfer, film patterning, and property tuning / modification. Third, the methods for integrating 2D van der Waals heterostructures are also discussed and summarized. Finally, the current challenges and future perspectives are highlighted.

Microfluidic sensors based on two-dimensional materials for chemical and biological assessments

There has been an exponential increase in the number of studies of two-dimensional (2D) layered materials for sensing applications since the isolation of graphene in 2004. These materials serve as...

Making high-quality quantum microwave devices with van der Waals superconductors

Ultra low-loss microwave materials are crucial for enhancing quantum coherence and scalability of superconducting qubits. Van der Waals (vdW) heterostructure is an attractive platform for quantum devices due to the single-crystal structure of the constituent two-dimensional (2D) layered materials and the lack of dangling bonds at their atomically sharp interfaces. However, new fabrication and characterization techniques are required to determine whether these structures can achieve low loss in the microwave regime. Here we report the fabrication of superconducting microwave resonators using NbSe$_2$ that achieve a quality factor $Q > 10^5$. This value sets an upper bound that corresponds to a resistance of $\leq 192 \mu\Omega$ when considering the additional loss introduced by integrating NbSe$_2$ into a standard transmon circuit. This work demonstrates the compatibility of 2D layered materials with high-quality microwave quantum devices.

Fabrication techniques for the integration of 2D materials

<p><a>With compact footprint, low energy consumption, high scalability, and mass producibility, chip-scale integrated devices are an indispensable part of modern technological change and development. Recent advances in </a>two-dimensional (2D) layered materials with their unique structures and distinctive properties have motivated their on-chip integration, yielding a variety of functional devices with superior performance and new features. To realize integrated devices incorporating 2D materials, it requires a diverse range of device fabrication techniques, which are of fundamental importance to achieve good performance and high reproducibility. This paper reviews the state-of-art fabrication techniques for the on-chip integration of 2D materials. First, an overview of the material properties and on-chip applications of 2D materials is provided. Second, different approaches used for integrating 2D materials on chips are comprehensively reviewed, which are categorized into material synthesis, on-chip transfer, film patterning, and property tuning / modification. Third, the methods for integrating 2D van der Waals heterostructures are also discussed and summarized. Finally, the current challenges and future perspectives are highlighted.</p> <p><b> </b></p>

Fabrication techniques for the integration of 2D materials

<p><a>With compact footprint, low energy consumption, high scalability, and mass producibility, chip-scale integrated devices are an indispensable part of modern technological change and development. Recent advances in </a>two-dimensional (2D) layered materials with their unique structures and distinctive properties have motivated their on-chip integration, yielding a variety of functional devices with superior performance and new features. To realize integrated devices incorporating 2D materials, it requires a diverse range of device fabrication techniques, which are of fundamental importance to achieve good performance and high reproducibility. This paper reviews the state-of-art fabrication techniques for the on-chip integration of 2D materials. First, an overview of the material properties and on-chip applications of 2D materials is provided. Second, different approaches used for integrating 2D materials on chips are comprehensively reviewed, which are categorized into material synthesis, on-chip transfer, film patterning, and property tuning / modification. Third, the methods for integrating 2D van der Waals heterostructures are also discussed and summarized. Finally, the current challenges and future perspectives are highlighted.</p> <p><b> </b></p>

Fabrication Methods for Integrating 2D Materials

With compact footprint, low energy consumption, high scalability, and mass producibility, chip-scale integrated devices are an indispensable part of modern technological change and development. Recent advances in two-dimensional (2D) layered materials with their unique structures and distinctive properties have motivated their on-chip integration, yielding a variety of functional devices with superior performance and new features. To realize integrated devices incorporating 2D materials, it requires a diverse range of device fabrication techniques, which are of fundamental importance to achieve good performance and high reproducibility. This paper reviews the state-of-art fabrication techniques for the on-chip integration of 2D materials. First, an overview of the material properties and on-chip applications of 2D materials is provided. Second, different approaches used for integrating 2D materials on chips are comprehensively reviewed, which are categorized into material synthesis, on-chip transfer, film patterning, and property tuning / modification. Third, the methods for integrating 2D van der Waals heterostructures are also discussed and summarized. Finally, the current challenges and future perspectives are highlighted.

Hybrid van der Waals heterojunction based on two-dimensional materials

Since the discovery of graphene, two-dimensional (2D) layered materials have always been the focus of material research. The layers of 2D materials are covalent bonds, and the layers are weakly bonded to adjacent layers through van der Waals (vdW) interactions. Since any dangling-bond-free surface could be combined with another material through vdW forces, the concept can be extended. This can refer to the integration of 2D materials with any other non-2D materials through non-covalent interactions. The emerging mixed-dimensional (2D+nD, where n is 0, 1 or 3) heterostructure devices has been studied and represents a wider range of vdW heterostructures. New electronic devices and optoelectronic devices based on such heterojunctions have unique functions. Therefore, this article depicts the research progress of (2D+nD, where n is 0, 1 or 3) vdW heterojunctions based on 2D materials.

An All-in-One Bio-inspired Neural Network

In spite of recent advancements in artificial neural networks (ANNs), the energy efficiency, multifunctionality, adaptability, and integrated nature of the biological neural networks largely remain unimitated in hardware neuromorphic computing systems. Here we exploit optoelectronic, computing, and programmable memory devices based on emerging two-dimensional (2D) layered materials such as MoS2 to demonstrate a monolithically integrated, multi-pixel, and “all-in-one” bio-inspired neural network (BNN) capable of sensing, encoding, learning, forgetting, and inferring at miniscule energy expenditure. We also demonstrate learning adaptability and stimulate learning challenges under specific synaptic conditions to mimic biological learning. Our findings highlight the potential of in-memory computing and sensing based on emerging 2D materials, devices, and integrated circuits not only to overcome the bottleneck of von Neumann computing in conventional CMOS designs but also aid in eliminating peripheral components necessary for competing technologies such as memristors.